Re: [PATCH 06/50] ppc/xive: Fix PHYS NSR ring matching

[Miles Glenn]

Reviewed-by: Glenn Miles <mil...@linux.ibm.com>

On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote:
> Test that the NSR exception bit field is equal to the pool ring value,
> rather than any common bits set, which is more correct (although there
> is no practical bug because the LSI NSR type is not implemented and
> POOL/PHYS NSR are encoded with exclusive bits).
> 
> Fixes: 4c3ccac636 ("pnv/xive: Add special handling for pool targets")
> Signed-off-by: Nicholas Piggin <npig...@gmail.com>
> ---
>  hw/intc/xive.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 80b07a0afe..cebe409a1a 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -54,7 +54,8 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t 
> ring)
>          uint8_t *alt_regs;
>  
>          /* POOL interrupt uses IPB in QW2, POOL ring */
> -        if ((ring == TM_QW3_HV_PHYS) && (nsr & (TM_QW3_NSR_HE_POOL << 6))) {
> +        if ((ring == TM_QW3_HV_PHYS) &&
> +            ((nsr & TM_QW3_NSR_HE) == (TM_QW3_NSR_HE_POOL << 6))) {
>              alt_ring = TM_QW2_HV_POOL;
>          } else {
>              alt_ring = ring;