Reviewed-by: Glenn Miles <mil...@linux.ibm.com>
On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote:
> The relationship between an interrupt signaled in the TIMA and the QEMU
> irq line to the processor to be 1:1, so they should be raised and
> lowered together and "just in case" lowering should be avoided (it could
> mask
>
> Signed-off-by: Nicholas Piggin <npig...@gmail.com>
> ---
> hw/intc/xive.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 4e0c71d684..d5dbeab6bd 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -95,8 +95,6 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring)
> g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0);
> g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0);
>
> - qemu_irq_lower(xive_tctx_output(tctx, sig_ring));
> -
> if (xive_nsr_indicates_exception(sig_ring, nsr)) {
> uint8_t cppr = sig_regs[TM_PIPR];
> uint8_t ring;
> @@ -117,6 +115,7 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t
> sig_ring)
>
> /* Clear the exception from NSR */
> sig_regs[TM_NSR] = 0;
> + qemu_irq_lower(xive_tctx_output(tctx, sig_ring));
>
> trace_xive_tctx_accept(tctx->cs->cpu_index, ring,
> regs[TM_IPB], sig_regs[TM_PIPR],
