On 9/3/25 14:51, Cédric Le Goater wrote:
From: Jamin Lin <jamin_...@aspeedtech.com>
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly defined registers.
Implemented "aspeed_intcio_read" and "aspeed_intcio_write" to handle
INTCIO-specific register access.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250307035945.3698802-18-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
---
include/hw/intc/aspeed_intc.h | 1 +
hw/intc/aspeed_intc.c | 112 ++++++++++++++++++++++++++++++++++
2 files changed, 113 insertions(+)
+static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset,
+ unsigned int size)
+{
+ AspeedINTCState *s = ASPEED_INTC(opaque);
+ const char *name = object_get_typename(OBJECT(s));
+ uint32_t reg = offset >> 2;
+ uint32_t value = 0;
+
+ value = s->regs[reg];
+ trace_aspeed_intc_read(name, offset, size, value);
+
+ return value;
+}
+static const MemoryRegionOps aspeed_intcio_ops = {
+ .read = aspeed_intcio_read,
+ .write = aspeed_intcio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
Could be safer to also add .impl.min_access_size = 4.
+};
