Nicholas Piggin <npig...@gmail.com> writes: > The e1000e and igb tests do not clear the ICR/EICR cause bits (or > set auto-clear) on seeing queue interrupts, which inhibits the > triggering of a new interrupt. The msix pending bit which is used > to test for the interrupt is also not cleared (the vector is masked). > > Fix this by clearing the ICR/EICR cause bits, and the msix pending > bit using the PBACLR device register. > > Cc: Michael S. Tsirkin <m...@redhat.com> > Cc: Marcel Apfelbaum <marcel.apfelb...@gmail.com> > Cc: Dmitry Fleytman <dmitry.fleyt...@gmail.com> > Cc: Akihiko Odaki <akihiko.od...@daynix.com> > Cc: Sriram Yagnaraman <sriram.yagnara...@ericsson.com> > Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Reviewed-by: Fabiano Rosas <faro...@suse.de>
