The following changes since commit 2af4a82ab2cce3412ffc92cd4c96bd870e33bc8e:
Merge tag 'pull-riscv-to-apply-20250519' of https://github.com/alistair23/qemu into staging (2025-05-19 14:00:54 -0400) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to fetch changes up to 220c739903cec99df032219ac94c45b5269a0ab5: qom: reverse order of instance_post_init calls (2025-05-20 08:18:53 +0200) ---------------------------------------------------------------- * target/riscv: clean up supported MMU modes, declarative CPU definitions, remove .instance_post_init (reviewed by Alistair) * qom: reverse order of instance_post_init calls * qapi/misc-target: doc and standard improvements for SGX * hw/pci-host/gt64120: Fix endianness handling * i386/hvf: Make CPUID_HT supported * i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported ---------------------------------------------------------------- Paolo Bonzini (27): hw/riscv: acpi: only create RHCT MMU entry for supported types target/riscv: assert argument to set_satp_mode_max_supported is valid target/riscv: cpu: store max SATP mode as a single integer target/riscv: update max_satp_mode based on QOM properties target/riscv: remove supported from RISCVSATPMap target/riscv: move satp_mode.{map,init} out of CPUConfig target/riscv: introduce RISCVCPUDef target/riscv: store RISCVCPUDef struct directly in the class target/riscv: merge riscv_cpu_class_init with the class_base function target/riscv: move RISCVCPUConfig fields to a header file target/riscv: include default value in cpu_cfg_fields.h.inc target/riscv: add more RISCVCPUDef fields target/riscv: convert abstract CPU classes to RISCVCPUDef target/riscv: convert profile CPU models to RISCVCPUDef target/riscv: convert bare CPU models to RISCVCPUDef target/riscv: convert dynamic CPU models to RISCVCPUDef target/riscv: convert SiFive E CPU models to RISCVCPUDef target/riscv: convert ibex CPU models to RISCVCPUDef target/riscv: convert SiFive U models to RISCVCPUDef target/riscv: th: make CSR insertion test a bit more intuitive target/riscv: generalize custom CSR functionality target/riscv: convert THead C906 to RISCVCPUDef target/riscv: convert TT Ascalon to RISCVCPUDef target/riscv: convert Ventana V1 to RISCVCPUDef target/riscv: convert Xiangshan Nanhu to RISCVCPUDef target/riscv: remove .instance_post_init qom: reverse order of instance_post_init calls Rakesh Jeyasingh (2): hw/pci-host/gt64120: Fix endianness handling hw/pci-host: Remove unused pci_host_data_be_ops Xiaoyao Li (2): i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported i386/hvf: Make CPUID_HT supported Zhao Liu (4): qapi/misc-target: Rename SGXEPCSection to SgxEpcSection qapi/misc-target: Rename SGXInfo to SgxInfo qapi/misc-target: Fix the doc related SGXEPCSection qapi/misc-target: Fix the doc to distinguish query-sgx and query-sgx-capabilities qapi/misc-target.json | 26 +- include/hw/pci-host/dino.h | 4 - include/hw/pci/pci_host.h | 1 - include/qom/object.h | 3 +- target/riscv/cpu-qom.h | 2 + target/riscv/cpu.h | 42 +- target/riscv/cpu_cfg.h | 178 +------ target/riscv/cpu_cfg_fields.h.inc | 170 +++++++ hw/i386/sgx-stub.c | 4 +- hw/i386/sgx.c | 32 +- hw/pci-host/gt64120.c | 82 +-- hw/pci/pci_host.c | 6 - hw/riscv/boot.c | 2 +- hw/riscv/virt-acpi-build.c | 15 +- hw/riscv/virt.c | 5 +- qom/object.c | 8 +- target/i386/cpu.c | 8 +- target/i386/hvf/x86_cpuid.c | 2 +- target/riscv/cpu.c | 1014 +++++++++++++++++-------------------- target/riscv/csr.c | 11 +- target/riscv/gdbstub.c | 6 +- target/riscv/kvm/kvm-cpu.c | 27 +- target/riscv/machine.c | 2 +- target/riscv/tcg/tcg-cpu.c | 13 +- target/riscv/th_csr.c | 30 +- target/riscv/translate.c | 2 +- 26 files changed, 821 insertions(+), 874 deletions(-) create mode 100644 target/riscv/cpu_cfg_fields.h.inc -- 2.49.0
