Wasm backend should implement its own disassember for Wasm
instructions.
Signed-off-by: Kohei Tokunaga <ktokunaga.m...@gmail.com>
---
tcg/wasm32.c | 243 +--------------------------------------------------
1 file changed, 1 insertion(+), 242 deletions(-)
diff --git a/tcg/wasm32.c b/tcg/wasm32.c
index 6de9b26b76..4bc53d76d0 100644
--- a/tcg/wasm32.c
+++ b/tcg/wasm32.c
@@ -831,246 +831,5 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
}
/*
- * Disassembler that matches the interpreter
+ * TODO: Disassembler is not implemented
*/
-
-static const char *str_r(TCGReg r)
-{
- static const char regs[TCG_TARGET_NB_REGS][4] = {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp"
- };
-
- QEMU_BUILD_BUG_ON(TCG_AREG0 != TCG_REG_R14);
- QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK != TCG_REG_R15);
-
- assert((unsigned)r < TCG_TARGET_NB_REGS);
- return regs[r];
-}
-
-static const char *str_c(TCGCond c)
-{
- static const char cond[16][8] = {
- [TCG_COND_NEVER] = "never",
- [TCG_COND_ALWAYS] = "always",
- [TCG_COND_EQ] = "eq",
- [TCG_COND_NE] = "ne",
- [TCG_COND_LT] = "lt",
- [TCG_COND_GE] = "ge",
- [TCG_COND_LE] = "le",
- [TCG_COND_GT] = "gt",
- [TCG_COND_LTU] = "ltu",
- [TCG_COND_GEU] = "geu",
- [TCG_COND_LEU] = "leu",
- [TCG_COND_GTU] = "gtu",
- [TCG_COND_TSTEQ] = "tsteq",
- [TCG_COND_TSTNE] = "tstne",
- };
-
- assert((unsigned)c < ARRAY_SIZE(cond));
- assert(cond[c][0] != 0);
- return cond[c];
-}
-
-/* Disassemble TCI bytecode. */
-int print_insn_tci(bfd_vma addr, disassemble_info *info)
-{
- const uint32_t *tb_ptr = (const void *)(uintptr_t)addr;
- const TCGOpDef *def;
- const char *op_name;
- uint32_t insn;
- TCGOpcode op;
- TCGReg r0, r1, r2, r3, r4;
- tcg_target_ulong i1;
- int32_t s2;
- TCGCond c;
- MemOpIdx oi;
- uint8_t pos, len;
- void *ptr;
-
- /* TCI is always the host, so we don't need to load indirect. */
- insn = *tb_ptr++;
-
- info->fprintf_func(info->stream, "%08x ", insn);
-
- op = extract32(insn, 0, 8);
- def = &tcg_op_defs[op];
- op_name = def->name;
-
- switch (op) {
- case INDEX_op_br:
- case INDEX_op_exit_tb:
- case INDEX_op_goto_tb:
- tci_args_l(insn, tb_ptr, &ptr);
- info->fprintf_func(info->stream, "%-12s %p", op_name, ptr);
- break;
-
- case INDEX_op_goto_ptr:
- tci_args_r(insn, &r0);
- info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0));
- break;
-
- case INDEX_op_call:
- tci_args_nl(insn, tb_ptr, &len, &ptr);
- info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr);
- break;
-
- case INDEX_op_brcond:
- tci_args_rl(insn, tb_ptr, &r0, &ptr);
- info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p",
- op_name, str_r(r0), ptr);
- break;
-
- case INDEX_op_setcond:
- case INDEX_op_tci_setcond32:
- tci_args_rrrc(insn, &r0, &r1, &r2, &c);
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
- op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c));
- break;
-
- case INDEX_op_tci_movi:
- tci_args_ri(insn, &r0, &i1);
- info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx,
- op_name, str_r(r0), i1);
- break;
-
- case INDEX_op_tci_movl:
- tci_args_rl(insn, tb_ptr, &r0, &ptr);
- info->fprintf_func(info->stream, "%-12s %s, %p",
- op_name, str_r(r0), ptr);
- break;
-
- case INDEX_op_tci_setcarry:
- info->fprintf_func(info->stream, "%-12s", op_name);
- break;
-
- case INDEX_op_ld8u:
- case INDEX_op_ld8s:
- case INDEX_op_ld16u:
- case INDEX_op_ld16s:
- case INDEX_op_ld32u:
- case INDEX_op_ld:
- case INDEX_op_st8:
- case INDEX_op_st16:
- case INDEX_op_st32:
- case INDEX_op_st:
- tci_args_rrs(insn, &r0, &r1, &s2);
- info->fprintf_func(info->stream, "%-12s %s, %s, %d",
- op_name, str_r(r0), str_r(r1), s2);
- break;
-
- case INDEX_op_bswap16:
- case INDEX_op_bswap32:
- case INDEX_op_ctpop:
- case INDEX_op_mov:
- case INDEX_op_neg:
- case INDEX_op_not:
- case INDEX_op_ext_i32_i64:
- case INDEX_op_extu_i32_i64:
- case INDEX_op_bswap64:
- tci_args_rr(insn, &r0, &r1);
- info->fprintf_func(info->stream, "%-12s %s, %s",
- op_name, str_r(r0), str_r(r1));
- break;
-
- case INDEX_op_add:
- case INDEX_op_addci:
- case INDEX_op_addcio:
- case INDEX_op_addco:
- case INDEX_op_and:
- case INDEX_op_andc:
- case INDEX_op_clz:
- case INDEX_op_ctz:
- case INDEX_op_divs:
- case INDEX_op_divu:
- case INDEX_op_eqv:
- case INDEX_op_mul:
- case INDEX_op_nand:
- case INDEX_op_nor:
- case INDEX_op_or:
- case INDEX_op_orc:
- case INDEX_op_rems:
- case INDEX_op_remu:
- case INDEX_op_rotl:
- case INDEX_op_rotr:
- case INDEX_op_sar:
- case INDEX_op_shl:
- case INDEX_op_shr:
- case INDEX_op_sub:
- case INDEX_op_subbi:
- case INDEX_op_subbio:
- case INDEX_op_subbo:
- case INDEX_op_xor:
- case INDEX_op_tci_ctz32:
- case INDEX_op_tci_clz32:
- case INDEX_op_tci_divs32:
- case INDEX_op_tci_divu32:
- case INDEX_op_tci_rems32:
- case INDEX_op_tci_remu32:
- case INDEX_op_tci_rotl32:
- case INDEX_op_tci_rotr32:
- tci_args_rrr(insn, &r0, &r1, &r2);
- info->fprintf_func(info->stream, "%-12s %s, %s, %s",
- op_name, str_r(r0), str_r(r1), str_r(r2));
- break;
-
- case INDEX_op_deposit:
- tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len);
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d",
- op_name, str_r(r0), str_r(r1), str_r(r2), pos, len);
- break;
-
- case INDEX_op_extract:
- case INDEX_op_sextract:
- tci_args_rrbb(insn, &r0, &r1, &pos, &len);
- info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d",
- op_name, str_r(r0), str_r(r1), pos, len);
- break;
-
- case INDEX_op_tci_movcond32:
- case INDEX_op_movcond:
- case INDEX_op_setcond2_i32:
- tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c);
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s",
- op_name, str_r(r0), str_r(r1), str_r(r2),
- str_r(r3), str_r(r4), str_c(c));
- break;
-
- case INDEX_op_muls2:
- case INDEX_op_mulu2:
- tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
- op_name, str_r(r0), str_r(r1),
- str_r(r2), str_r(r3));
- break;
-
- case INDEX_op_qemu_ld:
- case INDEX_op_qemu_st:
- tci_args_rrm(insn, &r0, &r1, &oi);
- info->fprintf_func(info->stream, "%-12s %s, %s, %x",
- op_name, str_r(r0), str_r(r1), oi);
- break;
-
- case INDEX_op_qemu_ld2:
- case INDEX_op_qemu_st2:
- tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
- info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s",
- op_name, str_r(r0), str_r(r1),
- str_r(r2), str_r(r3));
- break;
-
- case 0:
- /* tcg_out_nop_fill uses zeros */
- if (insn == 0) {
- info->fprintf_func(info->stream, "align");
- break;
- }
- /* fall through */
-
- default:
- info->fprintf_func(info->stream, "illegal opcode %d", op);
- break;
- }
-
- return sizeof(insn);
-}
--
2.43.0
