On Thu, May 08, 2025 at 12:01:03AM +0000, anisa.su...@gmail.com wrote:
> From: Anisa Su <anisa...@samsung.com>
>
> FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section
> 7.6.7.6.3
>
> Signed-off-by: Anisa Su <anisa...@samsung.com>
> ---
> hw/cxl/cxl-mailbox-utils.c | 97 ++++++++++++++++++++++++++++++++++++
> hw/mem/cxl_type3.c | 2 +-
> include/hw/cxl/cxl_device.h | 3 ++
> include/hw/cxl/cxl_mailbox.h | 6 +++
> include/hw/cxl/cxl_opcodes.h | 1 +
> 5 files changed, 108 insertions(+), 1 deletion(-)
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index 6afc45833d..fe38a13f71 100644
> --- a/hw/cxl/cxl-mailbox-utils.c
> +++ b/hw/cxl/cxl-mailbox-utils.c
> @@ -3426,6 +3426,96 @@ static CXLRetCode
> cmd_fm_get_host_dc_region_config(const struct cxl_cmd *cmd,
> return CXL_MBOX_SUCCESS;
> }
>
> +static void cxl_mbox_dc_event_create_record_hdr(CXLType3Dev *ct3d,
> + CXLEventRecordHdr *hdr)
> +{
> + /*
> + * CXL r3.1 section 8.2.9.2.1.6: Dynamic Capacity Event Record
> + *
> + * All Dynamic Capacity event records shall set the Event Record Severity
> + * field in the Common Event Record Format to Informational Event. All
> + * Dynamic Capacity related events shall be logged in the Dynamic
> Capacity
> + * Event Log.
> + */
> + uint8_t flags = 1 << CXL_EVENT_TYPE_INFO;
> +
> + st24_le_p(&hdr->flags, flags);
> + hdr->length = sizeof(struct CXLEventDynamicCapacity);
> + memcpy(&hdr->id, &dynamic_capacity_uuid, sizeof(hdr->id));
> + stq_le_p(&hdr->timestamp, cxl_device_get_timestamp(&ct3d->cxl_dstate));
> +}
This function does the same thing as cxl_assign_event_header(), maybe we
can move the cxl_assign_event_header() to header file so it can be used by
both cxl_type3.c and cxl-mailbox-utils.c and then this function is not
needed or simplified by calling cxl_assign_event_header().
Fan
> +
> +/* CXL r3.2 section 7.6.7.6.3: Set Host DC Region Configuration (Opcode
> 5602) */
> +static CXLRetCode cmd_fm_set_dc_region_config(const struct cxl_cmd *cmd,
> + uint8_t *payload_in,
> + size_t len_in,
> + uint8_t *payload_out,
> + size_t *len_out,
> + CXLCCI *cci)
> +{
> + struct {
> + uint8_t reg_id;
> + uint8_t rsvd[3];
> + uint64_t block_sz;
> + uint8_t flags;
> + uint8_t rsvd2[3];
> + } QEMU_PACKED *in = (void *)payload_in;
> + CXLType3Dev *ct3d = CXL_TYPE3(cci->d);
> + CXLEventDynamicCapacity dcEvent = {};
> + CXLDCRegion *region;
> +
> + region = &ct3d->dc.regions[in->reg_id];
> +
> + /*
> + * CXL r3.2 7.6.7.6.3: Set DC Region Configuration
> + * This command shall fail with Unsupported when the Sanitize on Release
> + * field does not match the region’s configuration... and the device
> + * does not support reconfiguration of the Sanitize on Release setting.
> + *
> + * Currently not reconfigurable, so always fail if sanitize bit
> + * doesn't match.
> + */
> + if ((in->flags & 0x1) != (region->flags & 0x1)) {
> + return CXL_MBOX_UNSUPPORTED;
> + }
> +
> + if (in->reg_id >= DCD_MAX_NUM_REGION) {
> + return CXL_MBOX_UNSUPPORTED;
> + }
> +
> + /* Check that no extents are in the region being reconfigured */
> + if (!bitmap_empty(region->blk_bitmap, region->len / region->block_size))
> {
> + return CXL_MBOX_UNSUPPORTED;
> + }
> +
> + /* Check that new block size is supported */
> + if (!test_bit(BIT((int) log2(in->block_sz)),
> + ®ion->supported_blk_size_bitmask)) {
> + return CXL_MBOX_INVALID_INPUT;
> + }
> +
> + /* Free bitmap and create new one for new block size. */
> + qemu_mutex_lock(®ion->bitmap_lock);
> + g_free(region->blk_bitmap);
> + region->blk_bitmap = bitmap_new(region->len / in->block_sz);
> + qemu_mutex_unlock(®ion->bitmap_lock);
> + region->block_size = in->block_sz;
If the new block size equals to region->block_size, we can avoid the free
and allocation of the bitmap?
Fan
> +
> + /* Create event record and insert into event log */
> + cxl_mbox_dc_event_create_record_hdr(ct3d, &dcEvent.hdr);
> + dcEvent.type = DC_EVENT_REGION_CONFIG_UPDATED;
> + dcEvent.validity_flags = 1;
> + dcEvent.host_id = 0;
> + dcEvent.updated_region_id = in->reg_id;
> +
> + if (cxl_event_insert(&ct3d->cxl_dstate,
> + CXL_EVENT_TYPE_DYNAMIC_CAP,
> + (CXLEventRecordRaw *)&dcEvent)) {
> + cxl_event_irq_assert(ct3d);
> + }
> + return CXL_MBOX_SUCCESS;
> +}
> +
> static const struct cxl_cmd cxl_cmd_set[256][256] = {
> [INFOSTAT][BACKGROUND_OPERATION_ABORT] = { "BACKGROUND_OPERATION_ABORT",
> cmd_infostat_bg_op_abort, 0, 0 },
> @@ -3552,6 +3642,13 @@ static const struct cxl_cmd
> cxl_cmd_set_fm_dcd[256][256] = {
> cmd_fm_get_dcd_info, 0, 0 },
> [FMAPI_DCD_MGMT][GET_HOST_DC_REGION_CONFIG] = {
> "GET_HOST_DC_REGION_CONFIG",
> cmd_fm_get_host_dc_region_config, 4, 0 },
> + [FMAPI_DCD_MGMT][SET_DC_REGION_CONFIG] = { "SET_DC_REGION_CONFIG",
> + cmd_fm_set_dc_region_config, 16,
> + (CXL_MBOX_CONFIG_CHANGE_COLD_RESET |
> + CXL_MBOX_CONFIG_CHANGE_CONV_RESET |
> + CXL_MBOX_CONFIG_CHANGE_CXL_RESET |
> + CXL_MBOX_IMMEDIATE_CONFIG_CHANGE |
> + CXL_MBOX_IMMEDIATE_DATA_CHANGE) },
> };
>
> /*
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index b5b3df5edf..edc29f1ccb 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1695,7 +1695,7 @@ void qmp_cxl_inject_correctable_error(const char *path,
> CxlCorErrorType type,
> pcie_aer_inject_error(PCI_DEVICE(obj), &err);
> }
>
> -static void cxl_assign_event_header(CXLEventRecordHdr *hdr,
> +void cxl_assign_event_header(CXLEventRecordHdr *hdr,
> const QemuUUID *uuid, uint32_t flags,
> uint8_t length, uint64_t timestamp)
> {
> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index 9cfd9c5a9f..22823e2054 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -821,4 +821,7 @@ void ct3_clear_region_block_backed(CXLType3Dev *ct3d,
> uint64_t dpa,
> uint64_t len);
> bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
> uint64_t len);
> +void cxl_assign_event_header(CXLEventRecordHdr *hdr,
> + const QemuUUID *uuid, uint32_t flags,
> + uint8_t length, uint64_t timestamp);
> #endif
> diff --git a/include/hw/cxl/cxl_mailbox.h b/include/hw/cxl/cxl_mailbox.h
> index 8e1c7c5f15..820c411cbb 100644
> --- a/include/hw/cxl/cxl_mailbox.h
> +++ b/include/hw/cxl/cxl_mailbox.h
> @@ -8,6 +8,7 @@
> #ifndef CXL_MAILBOX_H
> #define CXL_MAILBOX_H
>
> +#define CXL_MBOX_CONFIG_CHANGE_COLD_RESET (1)
> #define CXL_MBOX_IMMEDIATE_CONFIG_CHANGE (1 << 1)
> #define CXL_MBOX_IMMEDIATE_DATA_CHANGE (1 << 2)
> #define CXL_MBOX_IMMEDIATE_POLICY_CHANGE (1 << 3)
> @@ -15,6 +16,11 @@
> #define CXL_MBOX_SECURITY_STATE_CHANGE (1 << 5)
> #define CXL_MBOX_BACKGROUND_OPERATION (1 << 6)
> #define CXL_MBOX_BACKGROUND_OPERATION_ABORT (1 << 7)
> +#define CXL_MBOX_SECONDARY_MBOX_SUPPORTED (1 << 8)
> +#define CXL_MBOX_REQUEST_ABORT_BACKGROUND_OP_SUPPORTED (1 << 9)
> +#define CXL_MBOX_CEL_10_TO_11_VALID (1 << 10)
> +#define CXL_MBOX_CONFIG_CHANGE_CONV_RESET (1 << 11)
> +#define CXL_MBOX_CONFIG_CHANGE_CXL_RESET (1 << 12)
>
> #define CXL_LOG_CAP_CLEAR_SUPPORTED (1 << 0)
> #define CXL_LOG_CAP_POPULATE_SUPPORTED (1 << 1)
> diff --git a/include/hw/cxl/cxl_opcodes.h b/include/hw/cxl/cxl_opcodes.h
> index 68ad68291c..ed4be23b75 100644
> --- a/include/hw/cxl/cxl_opcodes.h
> +++ b/include/hw/cxl/cxl_opcodes.h
> @@ -64,5 +64,6 @@ enum {
> FMAPI_DCD_MGMT = 0x56,
> #define GET_DCD_INFO 0x0
> #define GET_HOST_DC_REGION_CONFIG 0x1
> + #define SET_DC_REGION_CONFIG 0x2
> GLOBAL_MEMORY_ACCESS_EP_MGMT = 0X59
> };
> --
> 2.47.2
>
--
Fan Ni
