Add CVA6 CPU type, for the OpenHW CVA6 cores
Signed-off-by: Ben Dooks <ben.do...@codethink.co.uk>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 4cfdb74891..b5460771d7 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -34,6 +34,7 @@
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
+#define TYPE_RISCV_CPU_CVA6 RISCV_CPU_TYPE_NAME("cva6")
#define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i")
#define TYPE_RISCV_CPU_RV32E RISCV_CPU_TYPE_NAME("rv32e")
#define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d92874baa0..0ad6a7b616 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -496,6 +496,24 @@ static void rv64_base_cpu_init(Object *obj)
#endif
}
+static void rv64_cva6_cpu_init(Object *obj)
+{
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
+
+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVS
| RVU);
+ env->priv_ver = PRIV_VERSION_1_12_0;
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
+#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_zifencei = true;
+ cpu->cfg.ext_zicsr = true;
+ cpu->cfg.mmu = true;
+ cpu->cfg.pmp = true;
+}
+
static void rv64_sifive_u_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
@@ -3247,6 +3265,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV64)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64,
rv64_base_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_CVA6, MXL_RV64,
rv64_cva6_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64,
rv64_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64,
rv64_sifive_u_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64,
rv64_sifive_u_cpu_init),
--
2.37.2.352.g3c44437643
