On Sun, May 25, 2025 at 05:02:15PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for EAR.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/microblaze/cpu.h | 2 +-
> target/microblaze/translate.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 6ad8643f2e..3ce28b302f 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -248,7 +248,7 @@ struct CPUArchState {
> uint32_t pc;
> uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */
> uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */
> - target_ulong ear;
> + uint64_t ear;
> uint32_t esr;
> uint32_t fsr;
> uint32_t btr;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 3d9756391e..b1fc9e5624 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1857,7 +1857,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> }
>
> qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n"
> - "ear=0x" TARGET_FMT_lx " slr=0x%x shr=0x%x\n",
> + "ear=0x%" PRIx64 " slr=0x%x shr=0x%x\n",
> env->esr, env->fsr, env->btr, env->edr,
> env->ear, env->slr, env->shr);
>
> --
> 2.43.0
>
