On Wed, May 21, 2025 at 7:21 PM Roan Richmond
<roan.richm...@codethink.co.uk> wrote:
>
Can you include in the commit message which exact version (please
include a link) of the spec this targets. We need exact versions as
RISC-V will often release multiple conflicting "final" versions, so
it's good to have a record of what this was written to support.
> Signed-off-by: Roan Richmond <roan.richm...@codethink.co.uk>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu_cfg.h | 1 +
> target/riscv/insn32.decode | 10 ++
> target/riscv/insn_trans/trans_rvzalasr.c.inc | 109 +++++++++++++++++++
> target/riscv/translate.c | 1 +
> 5 files changed, 122 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rvzalasr.c.inc
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d92874baa0..630911a289 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -121,6 +121,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_13_0, ext_zabha),
> ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
> ISA_EXT_DATA_ENTRY(zama16b, PRIV_VERSION_1_13_0, ext_zama16b),
> + ISA_EXT_DATA_ENTRY(zalasr, PRIV_VERSION_1_12_0, ext_zalasr),
> ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
> ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
> ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index cfe371b829..da23771899 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -96,6 +96,7 @@ struct RISCVCPUConfig {
> bool ext_zacas;
> bool ext_zama16b;
> bool ext_zabha;
> + bool ext_zalasr;
> bool ext_zalrsc;
> bool ext_zawrs;
> bool ext_zfa;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index cd23b1f3a9..c848c0c1c5 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -1066,3 +1066,13 @@ amominu_h 11000 . . ..... ..... 001 ..... 0101111
> @atom_st
> amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st
> amocas_b 00101 . . ..... ..... 000 ..... 0101111 @atom_st
> amocas_h 00101 . . ..... ..... 001 ..... 0101111 @atom_st
> +
> +# *** Zalasr Standard Extension ***
> +lb_aqrl 00110 . . ..... ..... 000 ..... 0101111 @atom_st
> +lh_aqrl 00110 . . ..... ..... 001 ..... 0101111 @atom_st
> +lw_aqrl 00110 . . ..... ..... 010 ..... 0101111 @atom_st
> +ld_aqrl 00110 . . ..... ..... 011 ..... 0101111 @atom_st
> +sb_aqrl 00111 . . ..... ..... 000 ..... 0101111 @atom_st
> +sh_aqrl 00111 . . ..... ..... 001 ..... 0101111 @atom_st
> +sw_aqrl 00111 . . ..... ..... 010 ..... 0101111 @atom_st
> +sd_aqrl 00111 . . ..... ..... 011 ..... 0101111 @atom_st
> diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc
> b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> new file mode 100644
> index 0000000000..7c39dd895c
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc
> @@ -0,0 +1,109 @@
> +/*
> + * RISC-V translation routines for the ZALASR (Load-Aquire and Store-Release)
> + * Extension.
> + *
> + * Copyright (c) 2025 Roan Richmond, roan.richm...@codethink.co.uk
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_ZALASR(ctx) do { \
> + if (!ctx->cfg_ptr->ext_zalasr) { \
> + return false; \
> + } \
> +} while (0)
> +
> +static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
> +{
> + decode_save_opc(ctx, 0);
> +
> + TCGv addr = get_address(ctx, a->rs1, 0);
> + TCGv dest = get_gpr(ctx, a->rd, EXT_NONE);
> + TCGBar bar = (a->rl) ? TCG_BAR_STRL : 0;
> +
> + memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
> +
> + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
> + gen_set_gpr(ctx, a->rd, dest);
> +
> + /* Add a memory barrier implied by AQ (mandatory) and RL (optional) */
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ | bar);
> +
> + return true;
> +}
> +
> +static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)
> +{
> + REQUIRE_ZALASR(ctx);
> + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_SB));
> +}
> +
> +static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)
> +{
> + REQUIRE_ZALASR(ctx);
> + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESW));
> +}
> +
> +static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)
> +{
> + REQUIRE_ZALASR(ctx);
> + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
> +{
> + REQUIRE_ZALASR(ctx);
There should be a RV64 check here
> + return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TEUQ));
> +}
> +
> +static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
> +{
> + decode_save_opc(ctx, 0);
> +
> + TCGv addr = get_address(ctx, a->rs1, 0);
> + TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
> + TCGBar bar = (a->aq) ? TCG_BAR_LDAQ : 0;
Aren't you missing a check to ensure RL is set?
Alistair
> +
> + memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
> +
> + /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */
> + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL | bar);
> +
> + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
> + return true;
> +}
> +
> +static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)
> +{
> + REQUIRE_ZALASR(ctx);
> + return gen_store_release(ctx, a, (MO_ALIGN | MO_SB));
> +}
> +
> +static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)
> +{
> + REQUIRE_ZALASR(ctx);
> + return gen_store_release(ctx, a, (MO_ALIGN | MO_TESW));
> +}
> +
> +static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)
> +{
> + REQUIRE_ZALASR(ctx);
> + return gen_store_release(ctx, a, (MO_ALIGN | MO_TESL));
> +}
> +
> +static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_ZALASR(ctx);
> + return gen_store_release(ctx, a, (MO_ALIGN | MO_TEUQ));
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 0d4f7d601c..558ea0646a 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1183,6 +1183,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase,
> target_ulong pc)
> #include "insn_trans/trans_rvzicond.c.inc"
> #include "insn_trans/trans_rvzacas.c.inc"
> #include "insn_trans/trans_rvzabha.c.inc"
> +#include "insn_trans/trans_rvzalasr.c.inc"
> #include "insn_trans/trans_rvzawrs.c.inc"
> #include "insn_trans/trans_rvzicbo.c.inc"
> #include "insn_trans/trans_rvzimop.c.inc"
> --
> 2.43.0
>
>
