On Sat, Jun 7, 2025 at 12:12 PM Chao Liu <chao....@yeah.net> wrote: > > Hi, > > Thanks to Daniel's testing, I have fixed this bug. > > PATCHv5: > > The differences are as follows: > > ``` > @@ -790,10 +790,11 @@ static void sifive_u_soc_realize(DeviceState *dev, > Error **errp) > MemoryRegion *mask_rom = g_new(MemoryRegion, 1); > MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); > char *plic_hart_config; > - int hartid_base = 1; > int i, j; > > qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); > - qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", hartid_base); > + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); > > ... > @@ -829,7 +829,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error > **errp) > > - plic_hart_config = riscv_plic_hart_config_string(hartid_base, > ms->smp.cpus); > + plic_hart_config = riscv_plic_hart_config_string(0, ms->smp.cpus); > ``` > > s->u_cpus use (ms->smp.cpus - 1), but plic_hart_config use ms->smp.cpus, > so the same hartid-base should not be used. > > Therefore, we should keep the original implementation here. > > PS: > > During my testing, I encountered a small issue, although riscv64_tuxrun passed > the test, it still displayed a timeout. When I removed my patch, > the result was still the same. > > PATCH v4: > > Rebasing this on > https://github.com/alistair23/qemu/tree/riscv-to-apply.next > > PATCH v3: > > Use cpu_by_arch_id() instead of qemu_get_cpu(), when registering gpio in > sifive_plic_create(). > > PATCH v2: > > During plic initialization, CPUSate is obtained by traversing qemu_get_cpu(), > which was an early design flaw (see PATCH v1 reviewed). > > A better approach is to use riscv's hartid for indexing via the > cpu_by_arch_id() > interface. > > PATCH v1 (Reviewed): > https://lore.kernel.org/qemu-riscv/416e68f4-bf12-4218-ae2d-0246cc8ea...@linaro.org/T/#u > > -- > Regards, > Chao > > Chao Liu (1): > hw/riscv: fix PLIC hart topology configuration string when not getting > CPUState correctly > > hw/intc/sifive_plic.c | 4 ++-- > hw/riscv/boot.c | 4 ++-- > hw/riscv/microchip_pfsoc.c | 2 +- > hw/riscv/sifive_u.c | 2 +- > hw/riscv/virt.c | 2 +- > include/hw/riscv/boot.h | 2 +- > 6 files changed, 8 insertions(+), 8 deletions(-)
Thanks! Applied to riscv-to-apply.next Alistair > > -- > 2.49.0 >
