On Tue, Jul 01, 2025 at 07:28:07PM +0200, Magnus Kulke wrote: > Hey all, > [...] > > Magnus Kulke (27): > accel: Add Meson and config support for MSHV accelerator > target/i386/emulate: Allow instruction decoding from stream > target/i386/mshv: Add x86 decoder/emu implementation > hw/intc: Generalize APIC helper names from kvm_* to accel_* > include/hw/hyperv: Add MSHV ABI header definitions > accel/mshv: Add accelerator skeleton > accel/mshv: Register memory region listeners > accel/mshv: Initialize VM partition > accel/mshv: Register guest memory regions with hypervisor > accel/mshv: Add ioeventfd support > accel/mshv: Add basic interrupt injection support > accel/mshv: Add vCPU creation and execution loop > accel/mshv: Add vCPU signal handling > target/i386/mshv: Add CPU create and remove logic > target/i386/mshv: Implement mshv_store_regs() > target/i386/mshv: Implement mshv_get_standard_regs() > target/i386/mshv: Implement mshv_get_special_regs() > target/i386/mshv: Implement mshv_arch_put_registers() > target/i386/mshv: Set local interrupt controller state > target/i386/mshv: Register CPUID entries with MSHV > target/i386/mshv: Register MSRs with MSHV > target/i386/mshv: Integrate x86 instruction decoder/emulator > target/i386/mshv: Write MSRs to the hypervisor > target/i386/mshv: Implement mshv_vcpu_run() > target/i386/mshv: Handle HVMSG_X64_HALT vm exit > accel/mshv: Workaround for overlappig mem mappings > docs: Add mshv to documentation
Thanks for posting this, Magnus. I skimmed through the code and found some cosmetic issues, but overall the code looks sensible to me. Wei
