On 6/20/2025 5:27 PM, Zhao Liu wrote:
> Refer to SDM vol.3 table 1-21, add the notes about the missing
> descriptor, and fix the typo and comment format.
>
> Signed-off-by: Zhao Liu <zhao1....@intel.com>
> ---
> target/i386/cpu.c | 31 ++++++++++++++++++++++---------
> 1 file changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 40aefb38f6da..e398868a3f8d 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -66,6 +66,7 @@ struct CPUID2CacheDescriptorInfo {
>
> /*
> * Known CPUID 2 cache descriptors.
> + * TLB, prefetch and sectored cache related descriptors are not included.
> * From Intel SDM Volume 2A, CPUID instruction
> */
> struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
> @@ -87,18 +88,29 @@ struct CPUID2CacheDescriptorInfo
> cpuid2_cache_descriptors[] = {
> .associativity = 2, .line_size = 64, },
> [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
> .associativity = 8, .line_size = 64, },
> - /* lines per sector is not supported cpuid2_cache_descriptor(),
> - * so descriptors 0x22, 0x23 are not included
> - */
> + /*
> + * lines per sector is not supported cpuid2_cache_descriptor(),
> + * so descriptors 0x22, 0x23 are not included
> + */
> [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
> .associativity = 16, .line_size = 64, },
> - /* lines per sector is not supported cpuid2_cache_descriptor(),
> - * so descriptors 0x25, 0x20 are not included
> - */
> + /*
> + * lines per sector is not supported cpuid2_cache_descriptor(),
> + * so descriptors 0x25, 0x29 are not included
> + */
> [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
> .associativity = 8, .line_size = 64, },
> [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
> .associativity = 8, .line_size = 64, },
> + /*
> + * Newer Intel CPUs (having the cores without L3, e.g., Intel MTL, ARL)
> + * use CPUID 0x4 leaf to describe cache topology, by encoding CPUID 0x2
> + * leaf with 0xFF. For older CPUs (without 0x4 leaf), it's also valid
> + * to just ignore l3's code if there's no l3.
s/l3/L3/g
Others look good to me.
Reviewed-by: Dapeng Mi <dapeng1...@linux.intel.com>
> + *
> + * This already covers all the cases in QEMU, so code 0x40 is not
> + * included.
> + */
> [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
> .associativity = 4, .line_size = 32, },
> [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
> @@ -136,9 +148,10 @@ struct CPUID2CacheDescriptorInfo
> cpuid2_cache_descriptors[] = {
> .associativity = 4, .line_size = 64, },
> [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
> .associativity = 4, .line_size = 64, },
> - /* lines per sector is not supported cpuid2_cache_descriptor(),
> - * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
> - */
> + /*
> + * lines per sector is not supported cpuid2_cache_descriptor(),
> + * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
> + */
> [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
> .associativity = 8, .line_size = 64, },
> [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
