On Wed, 2 Jul 2025 at 13:22, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> All F64MM instructions operate on a 256-bit vector.
> If only 128-bit vectors is supported by the cpu,
> then the cpu cannot enable F64MM.
>
> Suggested-by: Peter Maydell <peter.mayd...@linaro.org>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/cpu64.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 200da1c489..c5c289eadf 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -237,6 +237,12 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
> /* From now on sve_max_vq is the actual maximum supported length. */
> cpu->sve_max_vq = max_vq;
> cpu->sve_vq.map = vq_map;
> +
> + /* FEAT_F64MM requires the existence of a 256-bit vector size. */
> + if (max_vq < 2) {
> + cpu->isar.id_aa64zfr0 = FIELD_DP64(cpu->isar.id_aa64zfr0,
> + ID_AA64ZFR0, F64MM, 0);
> + }
> }
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
(with, as you say, the obvious fixup for the id register changes)
thanks
-- PMM
