Changes for v4:
- Combined with "target/arm: SME1/SVE2 fixes".
- Updated for IDREG changes.
- Introduced vectors_overlap() in sme_helper.c,
for use with the multi-vector operations.
- Various H() macro adjustments per review.
- Dropped the premature optimization in PMOV.
- Reorg WHILE patches to not break whilegt in the middle.
- Replace DecodeCounter.stride with lg2_stride, and thus
multiply/divide with shifts.
Patches lacking review:
009-target-arm-Fix-bfdotadd_ebf-vs-nan-selection.patch
041-target-arm-Implemement-SME2-SDOT-UDOT-USDOT-SUDOT.patch
059-target-arm-Implement-SME2-SQCVT-UQCVT-SQCVTU.patch
061-target-arm-Implement-SME2-SUNPK-UUNPK.patch
064-target-arm-Implement-SME2-SQRSHR-UQRSHR-SQRSHRN.patch
070-target-arm-Introduce-pred_count_test.patch
072-target-arm-Expand-do_zero-inline.patch (new)
074-target-arm-Split-out-do_whileg-from-helper_sve_wh.patch
090-target-arm-Implement-PMOV-for-SME2p1-SVE2p1.patch
108-tests-tcg-aarch64-Add-sme2-matmul-test-case.patch
r~
Peter Maydell (4):
target/arm: Rename FMOPA_h to FMOPA_w_h
target/arm: Rename BFMOPA to BFMOPA_w
target/arm: Implement FMOPA (non-widening) for fp16
target/arm: Implement SME2 BFMOPA (non-widening)
Richard Henderson (104):
target/arm: Fix SME vs AdvSIMD exception priority
target/arm: Fix sve_access_check for SME
target/arm: Fix 128-bit element ZIP, UZP, TRN
target/arm: Replace @rda_rn_rm_e0 in sve.decode
target/arm: Fix FMMLA (64-bit element) for 128-bit VL
target/arm: Disable FEAT_F64MM if maximum SVE vector size too small
target/arm: Fix PSEL size operands to tcg_gen_gvec_ands
target/arm: Fix f16_dotadd vs nan selection
target/arm: Fix bfdotadd_ebf vs nan selection
target/arm: Remove CPUARMState.vfp.scratch
target/arm: Introduce FPST_ZA, FPST_ZA_F16
target/arm: Use FPST_ZA for sme_fmopa_[hsd]
target/arm: Rename zarray to za_state.za
target/arm: Add isar feature tests for SME2p1, SVE2p1
target/arm: Add ZT0
target/arm: Add zt0_excp_el to DisasContext
target/arm: Implement SME2 ZERO ZT0
target/arm: Add alignment argument to gen_sve_{ldr,str}
target/arm: Implement SME2 LDR/STR ZT0
target/arm: Implement SME2 MOVT
target/arm: Split get_tile_rowcol argument tile_index
target/arm: Rename MOVA for translate
target/arm: Split out get_zarray
target/arm: Introduce ARMCPU.sme_max_vq
target/arm: Implement SME2 MOVA to/from tile, multiple registers
target/arm: Implement SME2 MOVA to/from array, multiple registers
target/arm: Implement SME2 BMOPA
target/arm: Implement SME2 SMOPS, UMOPS (2-way)
target/arm: Introduce gen_gvec_sve2_sqdmulh
target/arm: Implement SME2 Multiple and Single SVE Destructive
target/arm: Implement SME2 Multiple Vectors SVE Destructive
target/arm: Implement SME2 ADD/SUB (array results, multiple and single
vector)
target/arm: Implement SME2 ADD/SUB (array results, multiple vectors)
target/arm: Pass ZA to helper_sve2_fmlal_zz[zx]w_s
target/arm: Add helper_gvec{_ah}_bfmlsl{_nx}
target/arm: Implement SME2 FMLAL, BFMLAL
target/arm: Implement SME2 FDOT
target/arm: Implement SME2 BFDOT
target/arm: Implement SME2 FVDOT, BFVDOT
target/arm: Rename helper_gvec_*dot_[bh] to *_4[bh]
target/arm: Implemement SME2 SDOT, UDOT, USDOT, SUDOT
target/arm: Rename SVE SDOT and UDOT patterns
target/arm: Tighten USDOT (vectors) decode
target/arm: Implement SDOT, UDOT (2-way) for SME2/SVE2p1
target/arm: Implement SME2 SVDOT, UVDOT, SUVDOT, USVDOT
target/arm: Implement SME2 SMLAL, SMLSL, UMLAL, UMLSL
target/arm: Rename gvec_fml[as]_[hs] with _nf_ infix
target/arm: Implement SME2 FMLA, FMLS
target/arm: Implement SME2 BFMLA, BFMLS
target/arm: Implement SME2 FADD, FSUB, BFADD, BFSUB
target/arm: Implement SME2 ADD/SUB (array accumulator)
target/arm: Implement SME2 BFCVT, BFCVTN, FCVT, FCVTN
target/arm: Implement SME2 FCVT (widening), FCVTL
target/arm: Implement SME2 FCVTZS, FCVTZU
target/arm: Implement SME2 SCVTF, UCVTF
target/arm: Implement SME2 FRINTN, FRINTP, FRINTM, FRINTA
target/arm: Introduce do_[us]sat_[bhs] macros
target/arm: Use do_[us]sat_[bhs] in sve_helper.c
target/arm: Implement SME2 SQCVT, UQCVT, SQCVTU
target/arm: Implement SQCVTN, UQCVTN, SQCVTUN for SME2/SVE2p1
target/arm: Implement SME2 SUNPK, UUNPK
target/arm: Implement SME2 ZIP, UZP (four registers)
target/arm: Move do_urshr, do_srshr to vec_internal.h
target/arm: Implement SME2 SQRSHR, UQRSHR, SQRSHRN
target/arm: Implement SME2 ZIP, UZP (two registers)
target/arm: Implement SME2 FCLAMP, SCLAMP, UCLAMP
target/arm: Enable SCLAMP, UCLAMP for SVE2p1
target/arm: Implement FCLAMP for SME2, SVE2p1
target/arm: Implement SME2p1 Multiple Zero
target/arm: Introduce pred_count_test
target/arm: Fold predtest_ones into helper_sve_brkns
target/arm: Expand do_zero inline
target/arm: Split out do_whilel from helper_sve_whilel
target/arm: Split out do_whileg from helper_sve_whileg
target/arm: Move scale by esz into helper_sve_while*
target/arm: Split trans_WHILE to lt and gt
target/arm: Enable PSEL for SVE2p1
target/arm: Implement SVE2p1 WHILE (predicate pair)
target/arm: Implement SVE2p1 WHILE (predicate as counter)
target/arm: Implement SVE2p1 PTRUE (predicate as counter)
target/arm: Implement {ADD,SMIN,SMAX,UMIN,UMAX}QV for SVE2p1
target/arm: Implement SVE2p1 PEXT
target/arm: Implement SME2 SEL
target/arm: Implement ANDQV, ORQV, EORQV for SVE2p1
target/arm: Implement FADDQV, F{MIN,MAX}{NM}QV for SVE2p1
target/arm: Implement BFMLSLB{L,T} for SME2/SVE2p1
target/arm: Implement CNTP (predicate as counter) for SME2/SVE2p1
target/arm: Implement DUPQ for SME2p1/SVE2p1
target/arm: Implement EXTQ for SME2p1/SVE2p1
target/arm: Implement PMOV for SME2p1/SVE2p1
target/arm: Implement ZIPQ, UZPQ for SME2p1/SVE2p1
target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1
target/arm: Implement SME2 counted predicate register load/store
target/arm: Split the ST_zpri and ST_zprr patterns
target/arm: Implement {LD1,ST1}{W,D} (128-bit element) for SVE2p1
target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h
target/arm: Implement {LD,ST}[234]Q for SME2p1/SVE2p1
target/arm: Implement LD1Q, ST1Q for SVE2p1
target/arm: Implement MOVAZ for SME2p1
target/arm: Implement LUTI2, LUTI4 for SME2/SME2p1
target/arm: Support FPCR.AH in SME FMOPS, BFMOPS
target/arm: Enable FEAT_SME2p1 on -cpu max
linux-user/aarch64: Set hwcap bits for SME2p1/SVE2p1
tests/tcg/aarch64: Add sme2-matmul test case
target/arm/cpu-features.h | 63 ++
target/arm/cpu.h | 70 +-
target/arm/syndrome.h | 1 +
target/arm/tcg/helper-sme.h | 215 +++-
target/arm/tcg/helper-sve.h | 212 ++++
target/arm/tcg/helper.h | 91 +-
target/arm/tcg/sve_ldst_internal.h | 89 ++
target/arm/tcg/translate-a64.h | 10 +-
target/arm/tcg/translate.h | 9 +
target/arm/tcg/vec_internal.h | 148 +++
linux-user/aarch64/signal.c | 4 +-
linux-user/elfload.c | 8 +
target/arm/cpu.c | 11 +-
target/arm/cpu64.c | 8 +
target/arm/helper.c | 8 +-
target/arm/machine.c | 22 +-
target/arm/tcg/cpu64.c | 10 +-
target/arm/tcg/gengvec64.c | 11 +
target/arm/tcg/helper-a64.c | 2 +
target/arm/tcg/hflags.c | 34 +-
target/arm/tcg/mve_helper.c | 21 -
target/arm/tcg/neon_helper.c | 30 +
target/arm/tcg/sme_helper.c | 1674 +++++++++++++++++++++++++---
target/arm/tcg/sve_helper.c | 1201 ++++++++++++++++----
target/arm/tcg/translate-a64.c | 45 +-
target/arm/tcg/translate-neon.c | 18 +-
target/arm/tcg/translate-sme.c | 1480 +++++++++++++++++++++++-
target/arm/tcg/translate-sve.c | 1019 ++++++++++++++---
target/arm/tcg/vec_helper.c | 384 ++++++-
target/arm/tcg/vfp_helper.c | 12 +-
tests/tcg/aarch64/sme2-matmul-0.c | 236 ++++
docs/system/arm/emulation.rst | 6 +
target/arm/tcg/sme.decode | 937 +++++++++++++++-
target/arm/tcg/sve.decode | 327 +++++-
tests/tcg/aarch64/Makefile.target | 11 +-
tests/tcg/aarch64/sme2-matmul-1.S | 321 ++++++
36 files changed, 8041 insertions(+), 707 deletions(-)
create mode 100644 tests/tcg/aarch64/sme2-matmul-0.c
create mode 100644 tests/tcg/aarch64/sme2-matmul-1.S
--
2.43.0
