Complete the conversion of all routines in ptw.c from
MMUAccessType access_type to an access_perm bitmask.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/internals.h | 4 ++--
target/arm/ptw.c | 4 ++--
target/arm/tcg/m_helper.c | 8 ++++----
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 20b49201cb..0844048ee8 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1559,7 +1559,7 @@ typedef struct GetPhysAddrResult {
* get_phys_addr: get the physical address for a virtual address
* @env: CPUARMState
* @address: virtual address to get physical address for
- * @access_type: 0 for read, 1 for write, 2 for execute
+ * @access_perm: PAGE_{READ,WRITE,EXEC}, or 0
* @memop: memory operation feeding this access, or 0 for none
* @mmu_idx: MMU index indicating required translation regime
* @result: set on translation success.
@@ -1579,7 +1579,7 @@ typedef struct GetPhysAddrResult {
* value.
*/
bool get_phys_addr(CPUARMState *env, vaddr address,
- MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx,
+ unsigned access_perm, MemOp memop, ARMMMUIdx mmu_idx,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
__attribute__((nonnull));
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 19e67fba67..fe005622da 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -3619,7 +3619,7 @@ arm_mmu_idx_to_security_space(CPUARMState *env, ARMMMUIdx
mmu_idx)
}
bool get_phys_addr(CPUARMState *env, vaddr address,
- MMUAccessType access_type, MemOp memop, ARMMMUIdx mmu_idx,
+ unsigned access_perm, MemOp memop, ARMMMUIdx mmu_idx,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
S1Translate ptw = {
@@ -3627,7 +3627,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address,
.in_space = arm_mmu_idx_to_security_space(env, mmu_idx),
};
- return get_phys_addr_gpc(env, &ptw, address, 1 << access_type,
+ return get_phys_addr_gpc(env, &ptw, address, access_perm,
memop, result, fi);
}
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
index e52ab261be..454ee187a7 100644
--- a/target/arm/tcg/m_helper.c
+++ b/target/arm/tcg/m_helper.c
@@ -221,7 +221,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr,
uint32_t value,
int exc;
bool exc_secure;
- if (get_phys_addr(env, addr, MMU_DATA_STORE, 0, mmu_idx, &res, &fi)) {
+ if (get_phys_addr(env, addr, PAGE_WRITE, 0, mmu_idx, &res, &fi)) {
/* MPU/SAU lookup failed */
if (fi.type == ARMFault_QEMU_SFault) {
if (mode == STACK_LAZYFP) {
@@ -310,7 +310,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest,
uint32_t addr,
bool exc_secure;
uint32_t value;
- if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) {
+ if (get_phys_addr(env, addr, PAGE_READ, 0, mmu_idx, &res, &fi)) {
/* MPU/SAU lookup failed */
if (fi.type == ARMFault_QEMU_SFault) {
qemu_log_mask(CPU_LOG_INT,
@@ -2008,7 +2008,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx
mmu_idx, bool secure,
"...really SecureFault with SFSR.INVEP\n");
return false;
}
- if (get_phys_addr(env, addr, MMU_INST_FETCH, 0, mmu_idx, &res, &fi)) {
+ if (get_phys_addr(env, addr, PAGE_EXEC, 0, mmu_idx, &res, &fi)) {
/* the MPU lookup failed */
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK;
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure);
@@ -2044,7 +2044,7 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx
mmu_idx,
ARMMMUFaultInfo fi = {};
uint32_t value;
- if (get_phys_addr(env, addr, MMU_DATA_LOAD, 0, mmu_idx, &res, &fi)) {
+ if (get_phys_addr(env, addr, PAGE_READ, 0, mmu_idx, &res, &fi)) {
/* MPU/SAU lookup failed */
if (fi.type == ARMFault_QEMU_SFault) {
qemu_log_mask(CPU_LOG_INT,
--
2.43.0
