On 7/4/25 4:19 PM, Cornelia Huck wrote:
> Signed-off-by: Cornelia Huck <coh...@redhat.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Eric
> ---
> target/arm/cpu-sysregs.h.inc | 2 ++
> target/arm/cpu.h | 2 --
> target/arm/helper.c | 4 ++--
> target/arm/tcg/cpu64.c | 16 ++++++++--------
> 4 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
> index b96a35880430..44c877245eea 100644
> --- a/target/arm/cpu-sysregs.h.inc
> +++ b/target/arm/cpu-sysregs.h.inc
> @@ -4,6 +4,8 @@ DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
> DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
> DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
> DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
> +DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4)
> +DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5)
> DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
> DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
> DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index ca8ad1cc27a8..793c157d873e 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1066,8 +1066,6 @@ struct ArchCPU {
> uint32_t reset_sctlr;
> uint64_t pmceid0;
> uint64_t pmceid1;
> - uint64_t id_aa64afr0;
> - uint64_t id_aa64afr1;
> uint64_t clidr;
> uint64_t mp_affinity; /* MP ID without feature bits */
> /* The elements of this array are the CCSIDR values for each cache,
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 2f57ab4d87da..6acbb2bcd9bd 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -7983,12 +7983,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa64_tid3,
> - .resetvalue = cpu->id_aa64afr0 },
> + .resetvalue = GET_IDREG(isar, ID_AA64AFR0) },
> { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa64_tid3,
> - .resetvalue = cpu->id_aa64afr1 },
> + .resetvalue = GET_IDREG(isar, ID_AA64AFR1) },
> { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
> .access = PL1_R, .type = ARM_CP_CONST,
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 3f4fb003f440..00e12ed44ae8 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -428,8 +428,8 @@ static void aarch64_a64fx_initfn(Object *obj)
> SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000);
> SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408),
> SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000),
> - cpu->id_aa64afr0 = 0x0000000000000000;
> - cpu->id_aa64afr1 = 0x0000000000000000;
> + SET_IDREG(isar, ID_AA64AFR0, 0x0000000000000000);
> + SET_IDREG(isar, ID_AA64AFR1, 0x0000000000000000);
> SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122);
> SET_IDREG(isar, ID_AA64MMFR1, 0x0000000011212100);
> SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011);
> @@ -676,8 +676,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
> cpu->clidr = 0x82000023;
> cpu->ctr = 0xb444c004; /* With DIC and IDC set */
> cpu->dcz_blocksize = 4;
> - cpu->id_aa64afr0 = 0x00000000;
> - cpu->id_aa64afr1 = 0x00000000;
> + SET_IDREG(isar, ID_AA64AFR0, 0x00000000);
> + SET_IDREG(isar, ID_AA64AFR1, 0x00000000);
> SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull),
> SET_IDREG(isar, ID_AA64DFR1, 0x00000000),
> SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
> @@ -927,8 +927,8 @@ static void aarch64_a710_initfn(Object *obj)
> SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
> SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull);
> SET_IDREG(isar, ID_AA64DFR1, 0);
> - cpu->id_aa64afr0 = 0;
> - cpu->id_aa64afr1 = 0;
> + SET_IDREG(isar, ID_AA64AFR0, 0);
> + SET_IDREG(isar, ID_AA64AFR1, 0);
> SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
> SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull);
> SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101122ull);
> @@ -1029,8 +1029,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
> SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
> SET_IDREG(isar, ID_AA64DFR0, 0x000011f210305619ull);
> SET_IDREG(isar, ID_AA64DFR1, 0);
> - cpu->id_aa64afr0 = 0;
> - cpu->id_aa64afr1 = 0;
> + SET_IDREG(isar, ID_AA64AFR0, 0);
> + SET_IDREG(isar, ID_AA64AFR1, 0);
> SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and
> FEAT_RNG */
> SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull);
> SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101125ull);
