Hi Peter,

Sadly, I couldn't reorg mtedesc as I hypothesized, because of
different usage within AdvSIMD.  So I decided to expand the
mtedesc from 17 to 32 bits, and then pack the gvec desc and
mtedesc into a 64-bit argument.

Lightly tested so far, but it does fix the LD3Q/LD4Q assert.


r~


Richard Henderson (2):
  target/arm: Expand the descriptor for SME/SVE memory ops to i64
  target/arm: Pack mtedesc into upper 32 bits of descriptor

 target/arm/internals.h         |    8 +-
 target/arm/tcg/helper-sme.h    |  144 ++--
 target/arm/tcg/helper-sve.h    | 1196 ++++++++++++++++----------------
 target/arm/tcg/translate-a64.h |    2 +-
 target/arm/tcg/sme_helper.c    |   30 +-
 target/arm/tcg/sve_helper.c    |  145 ++--
 target/arm/tcg/translate-sme.c |    6 +-
 target/arm/tcg/translate-sve.c |   38 +-
 8 files changed, 772 insertions(+), 797 deletions(-)

-- 
2.43.0


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