This file needs definition of ARMCPU, and thus, belongs to hw/arm.
Signed-off-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
---
hw/{intc => arm}/armv7m_nvic.c | 0
hw/arm/meson.build | 1 +
hw/arm/trace-events | 17 +++++++++++++++++
hw/intc/meson.build | 1 -
hw/intc/trace-events | 17 -----------------
5 files changed, 18 insertions(+), 18 deletions(-)
rename hw/{intc => arm}/armv7m_nvic.c (100%)
diff --git a/hw/intc/armv7m_nvic.c b/hw/arm/armv7m_nvic.c
similarity index 100%
rename from hw/intc/armv7m_nvic.c
rename to hw/arm/armv7m_nvic.c
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 25b6bb438a2..68dbdd3e913 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -84,6 +84,7 @@ arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true:
files('vexpress.c'))
arm_common_ss.add(files('boot.c'))
arm_common_ss.add(when: 'CONFIG_ARM_GIC', if_true:
files('arm_gicv3_cpuif_common.c'))
arm_common_ss.add(when: 'CONFIG_ARM_GICV3', if_true:
files('arm_gicv3_cpuif.c'))
+arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
hw_arch += {'arm': arm_ss}
hw_common_arch += {'arm': arm_common_ss}
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index 250ad116186..e25fa32668c 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -62,6 +62,23 @@ gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int
hppvlpi, int grp, int prio)
gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3
CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d"
gicv3_cpuif_virt_set_maint_irq(uint32_t cpuid, int maintlevel) "GICv3 CPU i/f
0x%x virt HPPI update: setting maintenance-irq %d"
+# armv7m_nvic.c
+nvic_recompute_state(int vectpending, int vectpending_prio, int
exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d
exception_prio %d"
+nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int
vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d
is_s_banked %d vectpending_prio %d exception_prio %d"
+nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank
%d priority %d"
+nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level)
"NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
+nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d
to HardFault: insufficient priority %d >= %d"
+nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
+nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, int
en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d derived
%d (enabled: %d priority %d)"
+nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending
irq %d secure-bank %d (enabled: %d priority %d)"
+nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active
(prio %d)"
+nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d:
targets_secure: %d"
+nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)"
+nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d"
+nvic_set_nmi_level(int level) "NVIC external NMI level set to %d"
+nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg
read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
+nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg
write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
+
# omap1.c
omap1_pwl_clocking_scheme(const char *scheme) "omap1 CLKM: clocking scheme set
to %s"
omap1_pwl_backlight(int output) "omap1 PWL: backlight now at %d/256"
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 22814893cbe..dc857833dcb 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -40,7 +40,6 @@ endif
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true:
files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
-specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true:
files('loongson_liointc.c'))
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 4d6c886b794..aa9d65fdc25 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -165,23 +165,6 @@ gicv3_its_vte_read(uint32_t vpeid, int valid, uint32_t
vptsize, uint64_t vptaddr
gicv3_its_vte_read_fault(uint32_t vpeid) "GICv3 ITS: vPE Table read for vPEID
0x%x: faulted"
gicv3_its_vte_write(uint32_t vpeid, int valid, uint32_t vptsize, uint64_t
vptaddr, uint32_t rdbase) "GICv3 ITS: vPE Table write for vPEID 0x%x: valid %d
VPTsize 0x%x VPTaddr 0x%" PRIx64 " RDbase 0x%x"
-# armv7m_nvic.c
-nvic_recompute_state(int vectpending, int vectpending_prio, int
exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d
exception_prio %d"
-nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int
vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d
is_s_banked %d vectpending_prio %d exception_prio %d"
-nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank
%d priority %d"
-nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level)
"NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
-nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d
to HardFault: insufficient priority %d >= %d"
-nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
-nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, int
en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d derived
%d (enabled: %d priority %d)"
-nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending
irq %d secure-bank %d (enabled: %d priority %d)"
-nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active
(prio %d)"
-nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d:
targets_secure: %d"
-nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)"
-nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d"
-nvic_set_nmi_level(int level) "NVIC external NMI level set to %d"
-nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg
read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
-nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg
write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
-
# heathrow_pic.c
heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u:
0x%"PRIx64
heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" %u:
0x%"PRIx64
--
2.47.2
