On Wed, Jul 30, 2025 at 11:01 AM <alistai...@gmail.com> wrote: > > From: Alistair Francis <alistair.fran...@wdc.com> > > The following changes since commit 9b80226ece693197af8a981b424391b68b5bc38e: > > Update version for the v10.1.0-rc1 release (2025-07-29 13:00:41 -0400) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250730-2 > > for you to fetch changes up to 86bc3a0abf10072081cddd8dff25aa72c60e67b8: > > target/riscv: Restrict midelegh access to S-mode harts (2025-07-30 10:59:26 > +1000) > > ---------------------------------------------------------------- > Third RISC-V PR for 10.1 > > * Fix pmp range wraparound on zero > * Update FADT and MADT versions in ACPI tables > * Fix target register read when source is inactive > * Add riscv_hwprobe entry to linux-user strace list > * Do not call GETPC() in check_ret_from_m_mode() > * Revert "Generate strided vector loads/stores with tcg nodes." > * Fix exception type when VU accesses supervisor CSRs > * Restrict mideleg/medeleg/medelegh access to S-mode harts > * Restrict midelegh access to S-mode harts
Sorry about this being so large and late in the cycle. I just got back from parental leave and wanted to get these fixes in for 10.1 Alistair
