Add all C trace events (missing: baudrate)
Signed-off-by: Manos Pitsidianakis <manos.pitsidiana...@linaro.org>
---
rust/hw/char/pl011/src/device.rs | 28 +++++++++++++++++++++++---
rust/hw/char/pl011/src/lib.rs | 43 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
index
ceb71dd99b661b9f4da98f2dbabe18e82142035b..dabb4ffb5ed0b2df388ca266d3b549fe9cf6d7bc
100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -27,7 +27,14 @@
zeroable::Zeroable,
};
-use crate::registers::{self, Interrupt, RegisterOffset};
+use crate::{
+ registers::{self, Interrupt, RegisterOffset},
+ trace_events::{
+ trace_pl011_can_receive, trace_pl011_fifo_rx_full,
trace_pl011_fifo_rx_put,
+ trace_pl011_irq_state, trace_pl011_read, trace_pl011_read_fifo,
trace_pl011_receive,
+ trace_pl011_write,
+ },
+};
// TODO: You must disable the UART before any of the control registers are
// reprogrammed. When the UART is disabled in the middle of transmission or
@@ -305,6 +312,7 @@ fn read_data_register(&mut self, update: &mut bool) -> u32 {
}
self.receive_status_error_clear.set_from_data(c);
*update = true;
+ trace_pl011_read_fifo!(self.read_count, self.fifo_depth());
u32::from(c)
}
@@ -458,7 +466,9 @@ pub fn fifo_rx_put(&mut self, value: registers::Data) ->
bool {
self.read_fifo[slot] = value;
self.read_count += 1;
self.flags.set_receive_fifo_empty(false);
+ trace_pl011_fifo_rx_put!(value.into(), self.read_count, depth);
if self.read_count == depth {
+ trace_pl011_fifo_rx_full!();
self.flags.set_receive_fifo_full(true);
}
@@ -554,6 +564,7 @@ fn read(&self, offset: hwaddr, _size: u32) -> u64 {
self.update();
self.char_backend.accept_input();
}
+ trace_pl011_read!(offset, result, field);
result.into()
}
}
@@ -562,6 +573,7 @@ fn read(&self, offset: hwaddr, _size: u32) -> u64 {
fn write(&self, offset: hwaddr, value: u64, _size: u32) {
let mut update_irq = false;
if let Ok(field) = RegisterOffset::try_from(offset) {
+ trace_pl011_write!(offset, value, field);
// qemu_chr_fe_write_all() calls into the can_receive
// callback, so handle writes before entering PL011Registers.
if field == RegisterOffset::DR {
@@ -589,11 +601,20 @@ fn write(&self, offset: hwaddr, value: u64, _size: u32) {
fn can_receive(&self) -> u32 {
let regs = self.regs.borrow();
- // trace_pl011_can_receive(s->lcr, s->read_count, r);
- regs.fifo_depth() - regs.read_count
+ let fifo_depth = regs.fifo_depth();
+ let fifo_available = fifo_depth - regs.read_count;
+
+ trace_pl011_can_receive!(
+ regs.line_control.into(),
+ regs.read_count,
+ fifo_depth,
+ fifo_available
+ );
+ fifo_available
}
fn receive(&self, buf: &[u8]) {
+ trace_pl011_receive!(buf.len());
let mut regs = self.regs.borrow_mut();
if regs.loopback_enabled() {
// In loopback mode, the RX input signal is internally disconnected
@@ -642,6 +663,7 @@ fn reset_hold(&self, _type: ResetType) {
fn update(&self) {
let regs = self.regs.borrow();
let flags = regs.int_level & regs.int_enabled;
+ trace_pl011_irq_state!((flags != 0).into());
for (irq, i) in self.interrupts.iter().zip(IRQMASK) {
irq.set(flags.any_set(i));
}
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index
2b70d2ff5604179b367b91cbcfdbf9480fa30180..ecfbad27c80fc551a2ced2f9cfe2109b9142e26a
100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -19,3 +19,46 @@
pub const TYPE_PL011: &::std::ffi::CStr = c"pl011";
pub const TYPE_PL011_LUMINARY: &::std::ffi::CStr = c"pl011_luminary";
+
+#[qemu_api_macros::trace_events]
+pub mod trace_events {
+ fn pl011_irq_state(level: u32) {
+ "irq state {level}"
+ }
+
+ fn pl011_read(
+ addr: qemu_api::memory::hwaddr,
+ value: u32,
+ regname: crate::registers::RegisterOffset,
+ ) {
+ "addr {addr:#x} value {value:#x} reg {regname:?}"
+ }
+
+ fn pl011_read_fifo(rx_fifo_used: u32, rx_fifo_depth: u32) {
+ "RX FIFO read, used {rx_fifo_used}/{rx_fifo_depth}"
+ }
+
+ fn pl011_write(
+ addr: qemu_api::memory::hwaddr,
+ value: u64,
+ regname: crate::registers::RegisterOffset,
+ ) {
+ "addr {addr:#x} value {value:#x} reg {regname:?}"
+ }
+
+ fn pl011_can_receive(lcr: u32, rx_fifo_used: u32, rx_fifo_depth: u32,
rx_fifo_available: u32) {
+ "LCR {lcr:#x}, RX FIFO used {rx_fifo_used}/{rx_fifo_depth},
can_receive {rx_fifo_available} chars"
+ }
+
+ fn pl011_fifo_rx_put(c: u32, read_count: u32, rx_fifo_depth: u32) {
+ "RX FIFO push char [{c:#x}] {read_count}/{rx_fifo_depth} depth used"
+ }
+
+ fn pl011_fifo_rx_full() {
+ "RX FIFO now full, RXFF set"
+ }
+
+ fn pl011_receive(size: usize) {
+ "recv {size} chars"
+ }
+}
--
2.47.2
