On 17/7/25 11:38, Djordje Todorovic wrote:
This is needed for riscv based CPUs by MIPS since those may have sparse hart-ID layouts. ACLINT and APLIC still assume a dense range, and if a hart is missing, this causes NULL derefs.Signed-off-by: Chao-ying Fu <c...@mips.com> Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com> --- hw/intc/riscv_aclint.c | 21 +++++++++++++++++++-- hw/intc/riscv_aplic.c | 11 ++++++++--- 2 files changed, 27 insertions(+), 5 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index b0139f03f5..22ac4133d5 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -292,7 +292,13 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) s->timecmp = g_new0(uint64_t, s->num_harts); /* Claim timer interrupt bits */ for (i = 0; i < s->num_harts; i++) { - RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i)); + CPUState *cpu_by_hartid = cpu_by_arch_id(s->hartid_base + i); + if (cpu_by_hartid == NULL) { + qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid hartid: %u", + s->hartid_base + i);
DeviceRealize() handlers are part of machine modelling, not guest uses. IOW, triggering this is a programming mistake, so we should just abort() here.
