On 17/7/25 11:38, Djordje Todorovic wrote:
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu <c...@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com>
---
target/riscv/cpu.c | 3 +
target/riscv/cpu_cfg.h | 2 +-
target/riscv/cpu_cfg_fields.h.inc | 1 +
target/riscv/insn_trans/trans_xmips.c.inc | 84 +++++++++++++++++++++++
target/riscv/xmips.decode | 23 +++++++
5 files changed, 112 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 9734963035..f35d477f27 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -39,7 +39,7 @@ static inline bool always_true_p(const RISCVCPUConfig *cfg
__attribute__((__unus
static inline bool has_xmips_p(const RISCVCPUConfig *cfg)
{
- return cfg->ext_xmipscbop || cfg->ext_xmipscmov;
+ return cfg->ext_xmipscbop || cfg->ext_xmipscmov || cfg->ext_xmipslsp;
Checking for any XMIPS instruction implemented to return vendor
extension presence seems odd. Can you implement them separately?
