On 17/7/25 11:38, Djordje Todorovic wrote:
Introduce P8700 CPU by MIPS.
Signed-off-by: Chao-ying Fu <c...@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 15 +++++++++++++++
target/riscv/cpu_vendorid.h | 1 +
3 files changed, 17 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e584bdc5ac..401c0f6c7d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3180,6 +3180,21 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.max_satp_mode = VM_1_10_SV39,
),
Can we add the datasheet link here?
/* https://mips.com/products/hardware/p8700/ */
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MIPS_P8700, TYPE_RISCV_VENDOR_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
+ .priv_spec = PRIV_VERSION_1_12_0,
+ .cfg.max_satp_mode = VM_1_10_SV48,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zicsr = true,
+ .cfg.mmu = true,
+ .cfg.pmp = true,
+ .cfg.ext_zba = true,
+ .cfg.ext_zbb = true,
+ .cfg.marchid = 0x8000000000000201,
+ .cfg.mvendorid = MIPS_VENDOR_ID,
+ ),
