This extension has instructions for atomic 128-bit swap, fetch-and, and fetch-or. This is fairly easy to implement with existing host support for 128-bit compare-and-swap.
Unlike for 64-bit operations, I did not implement the multitude of atomic fetch-op and op-fetch functions. Those can wait until there is a need for them. r~ Richard Henderson (7): qemu/atomic: Finish renaming atomic128-cas.h headers qemu/atomic: Add atomic16 primitives for xchg, fetch_and, fetch_or accel/tcg: Add cpu_atomic_*_mmu for 16-byte xchg, fetch_and, fetch_or tcg: Add tcg_gen_atomic_{xchg,fetch_and,fetch_or}_i128 target/arm: Rename isar_feature_aa64_atomics target/arm: Implement FEAT_LSE128 target/arm: Enable FEAT_LSE128 for -cpu max accel/tcg/atomic_template.h | 80 +++++++++++++- accel/tcg/tcg-runtime.h | 12 +++ host/include/aarch64/host/atomic128-cas.h | 45 -------- include/accel/tcg/cpu-ldst-common.h | 13 ++- include/tcg/tcg-op-common.h | 7 ++ include/tcg/tcg-op.h | 3 + target/arm/cpu-features.h | 7 +- linux-user/elfload.c | 3 +- target/arm/tcg/cpu64.c | 2 +- target/arm/tcg/translate-a64.c | 73 ++++++++++--- tcg/tcg-op-ldst.c | 97 ++++++++++++++++- accel/tcg/atomic_common.c.inc | 9 ++ docs/system/arm/emulation.rst | 1 + host/include/aarch64/host/atomic128-cas.h.inc | 102 ++++++++++++++++++ host/include/generic/host/atomic128-cas.h.inc | 96 +++++++++++++++++ target/arm/tcg/a64.decode | 7 ++ 16 files changed, 487 insertions(+), 70 deletions(-) delete mode 100644 host/include/aarch64/host/atomic128-cas.h create mode 100644 host/include/aarch64/host/atomic128-cas.h.inc -- 2.43.0