Hi Paolo, Eric, Daniel, patch v3 changes: - Fix the get_log2 cunftion: https://lore.kernel.org/qemu-riscv/cover.1755287531.git.chao....@yeah.net/T/#t - Add test for vlsseg8e32 instruction. - Rebase on top of the latest master.
patch v2 changes: - Split the TCG node emulation of the complex strided load/store operation into two separate functions to simplify the implementation: https://lore.kernel.org/qemu-riscv/20250312155547.289642-1-paolo.sav...@embecosm.com/ Best regards, Chao Chao Liu (2): Generate strided vector loads/stores with tcg nodes. tests/tcg/riscv64: Add test for vlsseg8e32 instruction target/riscv/insn_trans/trans_rvv.c.inc | 326 ++++++++++++++++++---- tests/tcg/riscv64/Makefile.softmmu-target | 8 +- tests/tcg/riscv64/test-vlsseg8e32.S | 107 +++++++ 3 files changed, 389 insertions(+), 52 deletions(-) create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S -- 2.50.1