On Fri, 15 Aug 2025 at 13:29, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> This is FEAT_LSE -- rename the predicate to match.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/cpu-features.h | 2 +-
> linux-user/elfload.c | 2 +-
> target/arm/tcg/translate-a64.c | 24 ++++++++++++------------
> 3 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
> index 5876162428..e3d4c3d382 100644
> --- a/target/arm/cpu-features.h
> +++ b/target/arm/cpu-features.h
> @@ -406,7 +406,7 @@ static inline bool isar_feature_aa64_crc32(const
> ARMISARegisters *id)
> return FIELD_EX64_IDREG(id, ID_AA64ISAR0, CRC32) != 0;
> }
>
> -static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
> +static inline bool isar_feature_aa64_lse(const ARMISARegisters *id)
> {
> return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) != 0;
> }
The Arm ARM says that FEAT_LSE is for ATOMIC >= 2.
Older versions of the Arm ARM also say that the old name
ARMv8.1-Atomics was for >= 2, though, so this is something
we've always got wrong.
I just checked and all the CPUs we define do correctly set
the ATOMIC field to either 0 or 2 and not the reserved value
1, so we can add another patch that corrects this feature
function to do the correct check.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
