[RFC PATCH] tcg: Restrict qemu_ld2 and qemu_st2 opcodes to 32-bit hosts

[Philippe Mathieu-Daudé]

qemu_ld2 and qemu_st2 opcodes are band-aid for 32-bit hosts
and can't be reached on 64-bit ones. See in commit 3bedb9d3e28
("tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}") and 86fe5c2597c
("tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}") their constraint
is C_NotImplemented.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
 tcg/tcg.c | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index afac55a203a..ff1a8b71789 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1221,9 +1221,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
     OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
     OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
     OUTOP(INDEX_op_qemu_ld, TCGOutOpQemuLdSt, outop_qemu_ld),
-    OUTOP(INDEX_op_qemu_ld2, TCGOutOpQemuLdSt2, outop_qemu_ld2),
     OUTOP(INDEX_op_qemu_st, TCGOutOpQemuLdSt, outop_qemu_st),
-    OUTOP(INDEX_op_qemu_st2, TCGOutOpQemuLdSt2, outop_qemu_st2),
     OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems),
     OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu),
     OUTOP(INDEX_op_rotl, TCGOutOpBinary, outop_rotl),
@@ -1248,6 +1246,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
 
 #if TCG_TARGET_REG_BITS == 32
     OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2),
+    OUTOP(INDEX_op_qemu_ld2, TCGOutOpQemuLdSt2, outop_qemu_ld2),
+    OUTOP(INDEX_op_qemu_st2, TCGOutOpQemuLdSt2, outop_qemu_st2),
     OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2),
 #else
     OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64),
@@ -5829,17 +5829,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp 
*op)
         }
         break;
 
-    case INDEX_op_qemu_ld2:
-    case INDEX_op_qemu_st2:
-        {
-            const TCGOutOpQemuLdSt2 *out =
-                container_of(all_outop[op->opc], TCGOutOpQemuLdSt2, base);
-
-            out->out(s, type, new_args[0], new_args[1],
-                     new_args[2], new_args[3]);
-        }
-        break;
-
     case INDEX_op_brcond:
         {
             const TCGOutOpBrcond *out = &outop_brcond;
@@ -5887,6 +5876,16 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp 
*op)
         break;
 
 #if TCG_TARGET_REG_BITS == 32
+    case INDEX_op_qemu_ld2:
+    case INDEX_op_qemu_st2:
+        {
+            const TCGOutOpQemuLdSt2 *out =
+                container_of(all_outop[op->opc], TCGOutOpQemuLdSt2, base);
+
+            out->out(s, type, new_args[0], new_args[1],
+                     new_args[2], new_args[3]);
+        }
+        break;
     case INDEX_op_brcond2_i32:
         {
             const TCGOutOpBrcond2 *out = &outop_brcond2;
@@ -5912,6 +5911,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp 
*op)
         }
         break;
 #else
+    case INDEX_op_qemu_ld2:
+    case INDEX_op_qemu_st2:
     case INDEX_op_brcond2_i32:
     case INDEX_op_setcond2_i32:
         g_assert_not_reached();
-- 
2.51.0