On Wed, Aug 20, 2025 at 10:24:59AM +0200, Luc Michel wrote: > v2: > - Addressed formatting/typo issues [Francisco] > - Patch 23: GICv3 first-cpu-idx: addressed the KVM case by bailing > out if not 0 at realize. I chose this path as I don't have a clear > view of what it means to implement that for KVM. It seems to make > sense anyway as this property is meant to be used for modeling of > non-SMP systems. [Peter] > - Patch 39: added a comment to clarify cortex-a78ae != cortex-a78 [Peter] > > Hello, > > This series brings support for the AMD Versal Gen 2 (versal2) SoC in > QEMU. This SoC is the next iteration of the existing Versal SoC. > > It is organized as follows: > - The first patch is a fix in the Cadence GEM model. Some registers > were badly initialized when the device was built with a number of > priority queues greater than 2. This was confusing the Linux driver. > > - The next and biggest part of the series performs refactoring of the > existing versal SoC implementation. This consists in: > - splitting existing device types into base/concrete classes, > - moving from an in-place to dynamic device creation approach in > the SoC code for flexibility, > - describing the SoC using a new structure called VersalMap, > - moving the DTB creation logic in the SoC code itself alongside > device creation. > Patches are split such that each device is individually converted to > use this new approach. Behaviour changes are minimal and are > emphasised in the commit messages. This gets the SoC code ready for > versal2 addition and leverage the fact that Versal family SoCs are > quite similar in term of architecture. > > - versal2 SoC support is then added by adding the corresponding > VersalMap description. This allows to reuse the existing code > without duplication and almost no special case. > > - The amd-versal2-virt machine is finally added, following the same > idea as amd-versal-virt. The documentation and tests are updated > accordingly. > > Note that the xlnx-versal-virt machine is renamed amd-versal-virt to > follow current branding guidelines and stay coherent with the new > amd-versal2-virt machine. The xlnx-versal-virt name is kept as an alias > to amd-versal-virt for command line backward compatibility.
Hi Luc, I haven't looked at the details but overall it looks great! Nice to see that you found a way to share code between both Versal versions. Cheers, Edgar > > Thanks > > Luc > > Francisco Iglesias (1): > hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property > > Luc Michel (46): > hw/arm/xlnx-versal: split the xlnx-versal type > hw/arm/xlnx-versal: prepare for FDT creation > hw/arm/xlnx-versal: uart: refactor creation > hw/arm/xlnx-versal: canfd: refactor creation > hw/arm/xlnx-versal: sdhci: refactor creation > hw/arm/xlnx-versal: gem: refactor creation > hw/arm/xlnx-versal: adma: refactor creation > hw/arm/xlnx-versal: xram: refactor creation > hw/arm/xlnx-versal: usb: refactor creation > hw/arm/xlnx-versal: efuse: refactor creation > hw/arm/xlnx-versal: ospi: refactor creation > hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs > hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation > hw/arm/xlnx-versal: bbram: refactor creation > hw/arm/xlnx-versal: trng: refactor creation > hw/arm/xlnx-versal: rtc: refactor creation > hw/arm/xlnx-versal: cfu: refactor creation > hw/arm/xlnx-versal: crl: refactor creation > hw/arm/xlnx-versal-virt: virtio: refactor creation > hw/arm/xlnx-versal: refactor CPU cluster creation > hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping > hw/arm/xlnx-versal: instantiate the GIC ITS in the APU > hw/arm/xlnx-versal: add support for multiple GICs > hw/arm/xlnx-versal: add support for GICv2 > hw/arm/xlnx-versal: rpu: refactor creation > hw/arm/xlnx-versal: ocm: refactor creation > hw/arm/xlnx-versal: ddr: refactor creation > hw/arm/xlnx-versal: add the versal_get_num_cpu accessor > hw/misc/xlnx-versal-crl: remove unnecessary include directives > hw/misc/xlnx-versal-crl: split into base/concrete classes > hw/misc/xlnx-versal-crl: refactor device reset logic > hw/arm/xlnx-versal: reconnect the CRL to the other devices > hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices > hw/arm/xlnx-versal: tidy up > hw/misc/xlnx-versal-crl: add the versal2 version > hw/arm/xlnx-versal: add a per_cluster_gic switch to > VersalCpuClusterMap > hw/arm/xlnx-versal: add the target field in IRQ descriptor > target/arm/tcg/cpu64: add the cortex-a78ae CPU > hw/arm/xlnx-versal: add versal2 SoC > hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt > hw/arm/xlnx-versal-virt: split into base/concrete classes > hw/arm/xlnx-versal-virt: tidy up > docs/system/arm/xlnx-versal-virt: update supported devices > docs/system/arm/xlnx-versal-virt: add a note about dumpdtb > hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine > tests/functional/test_aarch64_xlnx_versal: test the versal2 machine > > docs/system/arm/xlnx-versal-virt.rst | 80 +- > include/hw/arm/xlnx-versal-version.h | 16 + > include/hw/arm/xlnx-versal.h | 341 +-- > include/hw/intc/arm_gicv3_common.h | 1 + > include/hw/misc/xlnx-versal-crl.h | 378 ++- > hw/arm/xlnx-versal-virt.c | 742 ++---- > hw/arm/xlnx-versal.c | 2460 +++++++++++++----- > hw/intc/arm_gicv3_common.c | 3 +- > hw/intc/arm_gicv3_cpuif.c | 2 +- > hw/intc/arm_gicv3_kvm.c | 6 + > hw/misc/xlnx-versal-crl.c | 602 ++++- > target/arm/tcg/cpu64.c | 79 + > tests/functional/test_aarch64_xlnx_versal.py | 10 +- > 13 files changed, 3060 insertions(+), 1660 deletions(-) > create mode 100644 include/hw/arm/xlnx-versal-version.h > > -- > 2.50.1 >
