On Thu, Aug 21, 2025 at 03:02:59PM +0200, Luc Michel wrote:
> v3:
> - Dropped qemu_get_cpu() usage in the machine code. Added an getter on
> the SoC interface to retrieve the boot CPU instead. [Phil]
> - Cleaned the mp_affinity logic. Drop the mask attribute and assume
> it's always 0xff (the Affx fields in MPIDR are 8 bits long). Use the
> ARM_AFFx_SHIFT constant instead of hardcoded values in .mp_affinity
> description. [Phil]
> - Avocado test renaming in patch 41 instead of 47. [Phil]
> - Documentation tweak. [Phil]
>
> v2:
> - Addressed formatting/typo issues [Francisco]
> - Patch 23: GICv3 first-cpu-idx: addressed the KVM case by bailing
> out if not 0 at realize. I chose this path as I don't have a clear
> view of what it means to implement that for KVM. It seems to make
> sense anyway as this property is meant to be used for modeling of
> non-SMP systems. [Peter]
> - Patch 39: added a comment to clarify cortex-a78ae != cortex-a78 [Peter]
>
> Hello,
>
> This series brings support for the AMD Versal Gen 2 (versal2) SoC in
> QEMU. This SoC is the next iteration of the existing Versal SoC.
>
> It is organized as follows:
> - The first and biggest part of the series performs refactoring of the
> existing versal SoC implementation. This consists in:
> - splitting existing device types into base/concrete classes,
> - moving from an in-place to dynamic device creation approach in
> the SoC code for flexibility,
> - describing the SoC using a new structure called VersalMap,
> - moving the DTB creation logic in the SoC code itself alongside
> device creation.
> Patches are split such that each device is individually converted to
> use this new approach. Behaviour changes are minimal and are
> emphasised in the commit messages. This gets the SoC code ready for
> versal2 addition and leverage the fact that Versal family SoCs are
> quite similar in term of architecture.
>
> - versal2 SoC support is then added by adding the corresponding
> VersalMap description. This allows to reuse the existing code
> without duplication and almost no special case.
>
> - The amd-versal2-virt machine is finally added, following the same
> idea as amd-versal-virt. The documentation and tests are updated
> accordingly.
>
> Note that the xlnx-versal-virt machine is renamed amd-versal-virt to
> follow current branding guidelines and stay coherent with the new
> amd-versal2-virt machine. The xlnx-versal-virt name is kept as an alias
> to amd-versal-virt for command line backward compatibility.
Hi Luc,
I run with this command-line:
qemu-system-aarch64 -M xlnx-versal-virt -m 2g -serial stdio -display none -net
nic,model=cadence_gem,netdev=n0 -netdev user,id=n0 -kernel Image -device
virtio-blk-device,drive=d0 -drive format=qcow2,if=none,file=rootfs.qcow2,id=d0
-append "root=/dev/vda1 console=ttyAMA0"
Before these patches, ethernet comes up fine but with this series
applied, ethernet stops working. The kernel finds device and the
driver comes up but it looks like it can't receive packets:
eth0 Link encap:Ethernet HWaddr 52:54:00:12:34:57
inet6 addr: fe80::5054:ff:fe12:3457/64 Scope:Link
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
--> RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:22 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:0 (0.0 B) TX bytes:4988 (4.8 KiB)
Interrupt:17
>
> Thanks
>
> Luc
>
>
> Francisco Iglesias (1):
> hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property
>
> Luc Michel (46):
> hw/arm/xlnx-versal: split the xlnx-versal type
> hw/arm/xlnx-versal: prepare for FDT creation
> hw/arm/xlnx-versal: uart: refactor creation
> hw/arm/xlnx-versal: canfd: refactor creation
> hw/arm/xlnx-versal: sdhci: refactor creation
> hw/arm/xlnx-versal: gem: refactor creation
> hw/arm/xlnx-versal: adma: refactor creation
> hw/arm/xlnx-versal: xram: refactor creation
> hw/arm/xlnx-versal: usb: refactor creation
> hw/arm/xlnx-versal: efuse: refactor creation
> hw/arm/xlnx-versal: ospi: refactor creation
> hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs
> hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation
> hw/arm/xlnx-versal: bbram: refactor creation
> hw/arm/xlnx-versal: trng: refactor creation
> hw/arm/xlnx-versal: rtc: refactor creation
> hw/arm/xlnx-versal: cfu: refactor creation
> hw/arm/xlnx-versal: crl: refactor creation
> hw/arm/xlnx-versal-virt: virtio: refactor creation
> hw/arm/xlnx-versal: refactor CPU cluster creation
> hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping
> hw/arm/xlnx-versal: instantiate the GIC ITS in the APU
> hw/arm/xlnx-versal: add support for multiple GICs
> hw/arm/xlnx-versal: add support for GICv2
> hw/arm/xlnx-versal: rpu: refactor creation
> hw/arm/xlnx-versal: ocm: refactor creation
> hw/arm/xlnx-versal: ddr: refactor creation
> hw/arm/xlnx-versal: add the versal_get_num_cpu accessor
> hw/misc/xlnx-versal-crl: remove unnecessary include directives
> hw/misc/xlnx-versal-crl: split into base/concrete classes
> hw/misc/xlnx-versal-crl: refactor device reset logic
> hw/arm/xlnx-versal: reconnect the CRL to the other devices
> hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices
> hw/arm/xlnx-versal: tidy up
> hw/misc/xlnx-versal-crl: add the versal2 version
> hw/arm/xlnx-versal: add a per_cluster_gic switch to
> VersalCpuClusterMap
> hw/arm/xlnx-versal: add the target field in IRQ descriptor
> target/arm/tcg/cpu64: add the cortex-a78ae CPU
> hw/arm/xlnx-versal: add versal2 SoC
> hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt
> hw/arm/xlnx-versal-virt: split into base/concrete classes
> hw/arm/xlnx-versal-virt: tidy up
> docs/system/arm/xlnx-versal-virt: update supported devices
> docs/system/arm/xlnx-versal-virt: add a note about dumpdtb
> hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine
> tests/functional/test_aarch64_xlnx_versal: test the versal2 machine
>
> docs/system/arm/xlnx-versal-virt.rst | 80 +-
> include/hw/arm/xlnx-versal-version.h | 16 +
> include/hw/arm/xlnx-versal.h | 342 +--
> include/hw/intc/arm_gicv3_common.h | 1 +
> include/hw/misc/xlnx-versal-crl.h | 378 ++-
> hw/arm/xlnx-versal-virt.c | 742 ++----
> hw/arm/xlnx-versal.c | 2455 +++++++++++++-----
> hw/intc/arm_gicv3_common.c | 3 +-
> hw/intc/arm_gicv3_cpuif.c | 2 +-
> hw/intc/arm_gicv3_kvm.c | 6 +
> hw/misc/xlnx-versal-crl.c | 602 ++++-
> target/arm/tcg/cpu64.c | 79 +
> tests/functional/test_aarch64_xlnx_versal.py | 12 +-
> 13 files changed, 3057 insertions(+), 1661 deletions(-)
> create mode 100644 include/hw/arm/xlnx-versal-version.h
>
> --
> 2.50.1
>
