This commit generates the mb operation. In Wasm, it uses the atomic.fence instruction as the fence operator [1]. TCI instruction is also generated in the same way as the original TCI backend using smp_mb().
[1] https://webassembly.github.io/threads/core/syntax/instructions.html#atomic-memory-instructions Signed-off-by: Kohei Tokunaga <ktokunaga.m...@gmail.com> --- tcg/wasm.c | 4 ++++ tcg/wasm/tcg-target.c.inc | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+) V2: - Added Wasm implementation of the mb operation using the atomic.fence instruction. diff --git a/tcg/wasm.c b/tcg/wasm.c index 793c1807c2..1cc2e45e77 100644 --- a/tcg/wasm.c +++ b/tcg/wasm.c @@ -566,6 +566,10 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env, const void *v_tb_ptr) taddr = regs[r1]; tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); break; + case INDEX_op_mb: + /* Ensure ordering for all kinds */ + smp_mb(); + break; default: g_assert_not_reached(); } diff --git a/tcg/wasm/tcg-target.c.inc b/tcg/wasm/tcg-target.c.inc index e1ee2f6485..1d639561db 100644 --- a/tcg/wasm/tcg-target.c.inc +++ b/tcg/wasm/tcg-target.c.inc @@ -1116,6 +1116,11 @@ static void tcg_out_op_r(TCGContext *s, TCGOpcode op, TCGReg r0) tcg_out32(s, insn); } +static void tcg_out_op_v(TCGContext *s, TCGOpcode op) +{ + tcg_out32(s, (uint8_t)op); +} + static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t i1) { tcg_insn_unit_tci insn = 0; @@ -1931,6 +1936,20 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) g_assert_not_reached(); } +static void tcg_out_mb(TCGContext *s, unsigned a0) +{ + tcg_out_op_v(s, INDEX_op_mb); + + /* + * Wasm's threading proposal provides atomic.fence instruction as the fence + * operator. + * https://webassembly.github.io/threads/core/syntax/instructions.html#atomic-memory-instructions + */ + tcg_wasm_out8(s, 0xfe); + tcg_wasm_out8(s, 0x03); + tcg_wasm_out8(s, 0x00); +} + static void tcg_out_tb_start(TCGContext *s) { init_sub_buf(); -- 2.43.0
