Processing of cp was split between add_cpreg_to_hashtable and
define_one_arm_cp_reg. Unify it all to the top-level function.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/helper.c | 53 +++++++++++++++++++--------------------------
1 file changed, 22 insertions(+), 31 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index da6a8f0a8f..a9d6ed1270 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7269,7 +7269,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
*/
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
CPState state, CPSecureState secstate,
- int crm, int opc1, int opc2,
+ int cp, int crm, int opc1, int opc2,
const char *name)
{
CPUARMState *env = &cpu->env;
@@ -7277,28 +7277,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
ARMCPRegInfo *r2;
bool is64 = r->type & ARM_CP_64BIT;
bool ns = secstate & ARM_CP_SECSTATE_NS;
- int cp = r->cp;
size_t name_len;
bool make_const;
switch (state) {
case ARM_CP_STATE_AA32:
- /* We assume it is a cp15 register if the .cp field is left unset. */
- if (cp == 0 && r->state == ARM_CP_STATE_BOTH) {
- cp = 15;
- }
key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
break;
case ARM_CP_STATE_AA64:
- /*
- * To allow abbreviation of ARMCPRegInfo definitions, we treat
- * cp == 0 as equivalent to the value for "standard guest-visible
- * sysreg". STATE_BOTH definitions are also always "standard sysreg"
- * in their AArch64 view (the .cp value may be non-zero for the
- * benefit of the AArch32 view).
- */
- assert(cp == 0 || r->state == ARM_CP_STATE_BOTH);
- cp = 0;
key = ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2);
break;
default:
@@ -7459,7 +7445,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
}
static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r,
- int crm, int opc1, int opc2)
+ int cp, int crm, int opc1, int opc2)
{
/*
* Under AArch32 CP registers can be common
@@ -7472,16 +7458,16 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu,
const ARMCPRegInfo *r,
switch (r->secure) {
case ARM_CP_SECSTATE_S:
case ARM_CP_SECSTATE_NS:
- add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32,
- r->secure, crm, opc1, opc2, r->name);
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure,
+ cp, crm, opc1, opc2, r->name);
break;
case ARM_CP_SECSTATE_BOTH:
name = g_strdup_printf("%s_S", r->name);
- add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32,
- ARM_CP_SECSTATE_S, crm, opc1, opc2, name);
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_S,
+ cp, crm, opc1, opc2, name);
g_free(name);
- add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32,
- ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name);
+ add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_NS,
+ cp, crm, opc1, opc2, r->name);
break;
default:
g_assert_not_reached();
@@ -7512,11 +7498,11 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu,
const ARMCPRegInfo *r,
nxs_ri.fgt |= R_FGT_NXS_MASK;
}
add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64,
- ARM_CP_SECSTATE_NS, crm, opc1, opc2, name);
+ ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, name);
}
add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS,
- crm, opc1, opc2, r->name);
+ 0, crm, opc1, opc2, r->name);
}
void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r)
@@ -7551,6 +7537,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const
ARMCPRegInfo *r)
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
+ int cp = r->cp;
/*
* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless.
@@ -7573,21 +7560,25 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const
ARMCPRegInfo *r)
*/
switch (r->state) {
case ARM_CP_STATE_BOTH:
- /* 0 has a special meaning, but otherwise the same rules as AA32. */
- if (r->cp == 0) {
+ /*
+ * If the cp field is left unset, assume cp15.
+ * Otherwise apply the same rules as AA32.
+ */
+ if (cp == 0) {
+ cp = 15;
break;
}
/* fall through */
case ARM_CP_STATE_AA32:
if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
!arm_feature(&cpu->env, ARM_FEATURE_M)) {
- assert(r->cp >= 14 && r->cp <= 15);
+ assert(cp >= 14 && cp <= 15);
} else {
- assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15));
+ assert(cp < 8 || (cp >= 14 && cp <= 15));
}
break;
case ARM_CP_STATE_AA64:
- assert(r->cp == 0);
+ assert(cp == 0);
break;
default:
g_assert_not_reached();
@@ -7657,13 +7648,13 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const
ARMCPRegInfo *r)
for (int opc2 = opc2min; opc2 <= opc2max; opc2++) {
switch (r->state) {
case ARM_CP_STATE_AA32:
- add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2);
+ add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc2);
break;
case ARM_CP_STATE_AA64:
add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2);
break;
case ARM_CP_STATE_BOTH:
- add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2);
+ add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc2);
add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2);
break;
default:
--
2.43.0
