[Stable-10.0.4 13/59] target/riscv: Fix exception type when VU accesses supervisor CSRs

[Michael Tokarev]

From: Xu Lu <luxu.ker...@bytedance.com>

When supervisor CSRs are accessed from VU-mode, a virtual instruction
exception should be raised instead of an illegal instruction.

Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking)
Signed-off-by: Xu Lu <luxu.ker...@bytedance.com>
Reviewed-by: Anup Patel <apa...@ventanamicro.com>
Reviewed-by: Nutty Liu <liujin...@lanxincomputing.com>
Message-ID: <20250708060720.7030-1-luxu.ker...@bytedance.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
(cherry picked from commit 30ef718423e8018723087cd17be0fd9c6dfa2e53)
Signed-off-by: Michael Tokarev <m...@tls.msk.ru>

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7948188356..f1c4c8c1b8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -5498,7 +5498,7 @@ static inline RISCVException 
riscv_csrrw_check(CPURISCVState *env,
 
     csr_priv = get_field(csrno, 0x300);
     if (!env->debugger && (effective_priv < csr_priv)) {
-        if (csr_priv == (PRV_S + 1) && env->virt_enabled) {
+        if (csr_priv <= (PRV_S + 1) && env->virt_enabled) {
             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
         }
         return RISCV_EXCP_ILLEGAL_INST;
-- 
2.47.2