This patch series introduces support for Zvqdotq extension. The Zvqdotq extension's ISA specification is not yet ratified, so this patch series is based on the latest draft (v0.0.2) and treats the Zvqdotq extension as an experimental extension.
The draft of the Zvqdotq ISA specification: https://github.com/riscv/riscv-dot-product Max Chou (3): target/riscv: Add Zvqdotq cfg property target/riscv: rvv: Add Zvqdotq support target/riscv: Expose Zvqdotq extension as a cpu property target/riscv/cpu.c | 2 + target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/helper.h | 10 +++ target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvzvqdotq.c.inc | 61 ++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 5 ++ target/riscv/translate.c | 1 + target/riscv/vector_helper.c | 63 +++++++++++++++++++ 8 files changed, 152 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvqdotq.c.inc -- 2.43.0
