Hi Cédric, Thank you for your help and the review. I’ll start a new thread to discuss the test script.
Best Regards, Kane > -----Original Message----- > From: Cédric Le Goater <c...@kaod.org> > Sent: Tuesday, September 2, 2025 1:44 PM > To: Kane Chen <kane_c...@aspeedtech.com>; Peter Maydell > <peter.mayd...@linaro.org>; Steven Lee <steven_...@aspeedtech.com>; Troy > Lee <leet...@gmail.com>; Jamin Lin <jamin_...@aspeedtech.com>; Andrew > Jeffery <and...@codeconstruct.com.au>; Joel Stanley <j...@jms.id.au>; > open list:ASPEED BMCs <qemu-...@nongnu.org>; open list:All patches CC > here <qemu-devel@nongnu.org> > Cc: Troy Lee <troy_...@aspeedtech.com> > Subject: Re: [SPAM] [PATCH v5 00/10] aspeed: OTP model, SBC integration, > tests, and docs > > Hello Kane, > > On 8/12/25 11:39, Kane Chen wrote: > > From: Kane-Chen-AS <kane_c...@aspeedtech.com> > > > > This patch series extends the QEMU model for the ASPEED OTP (One-Time > > Programmable) memory device with block backend support and tighter > > integration with the SoC and machine configuration. > > > > The OTP model simulates a simple fuse array used in ASPEED SoCs for > > secure boot, configuration, key storage, and user-programmable data. > > The updated model adds support for loading initial OTP content from a > > file via the QEMU CLI. > > > > Example usage: > > ./qemu-system-arm \ > > -machine ast2600-evb \ > > -blockdev driver=file,filename=otpmem.img,node-name=otp \ > > -global aspeed-otp.drive=otp \ > > ... > > > > Any feedback or suggestions are appreciated! > > > > Kane > > --- > > > > ChangeLog > > --------- > > v5: > > - Add OTP programming semantics and tracing > > - Integrate OTP into AST1030 SoC > > - Add CAMP2 register support for reading both DWORDs of OTP data > > entries > > - Handle voltage mode write commands to avoid misreporting valid > > requests as "Unknown command" > > - Add functional test to verify firmware boot with a pre-configured > > OTP image > > - Add documentation for OTP memory options in QEMU > > > > v4: > > - Add a 'drive' property to allow backing OTP data with a block device > > - Expose a machine parameter (`-machine otpmem=XXX`) for convenient > > aliasing of the OTP drive via QOM path > > > > v3: > > - Switched to object_property_set_int() for setting "size" > > - Simplified qdev_realize() error handling by passing errp directly > > - Added "drive" property to OTP model for future extensibility > > > > v2: > > - Rename device from 'aspeed_otpmem' to 'aspeed_otp' and move it to > > hw/nvram/ > > - Move OTP device realization from instance_init to the realize > > function > > - Improve error logging with qemu_log_mask() and remove unused error > > propagation > > > > v1: > > - Initial version > > > > --- > > > > Kane-Chen-AS (10): > > hw/nvram/aspeed_otp: Add ASPEED OTP memory device model > > hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC > > hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs > > hw/nvram/aspeed_otp: Add 'drive' property to support block backend > > hw/nvram/aspeed_otp: Add OTP programming semantics and tracing > > hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs > > hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads > > hw/misc/aspeed_sbc: Handle OTP write command for voltage mode > > registers > > tests/function/aspeed: Add OTP functional test > > docs/system/arm/aspeed: Document OTP memory options > > > > docs/system/arm/aspeed.rst | 31 ++++ > > include/hw/misc/aspeed_sbc.h | 6 + > > include/hw/nvram/aspeed_otp.h | 33 ++++ > > hw/arm/aspeed_ast10x0.c | 2 +- > > hw/arm/aspeed_ast2600.c | 2 +- > > hw/misc/aspeed_sbc.c | 196 > ++++++++++++++++++++++++ > > hw/nvram/aspeed_otp.c | 190 > +++++++++++++++++++++++ > > hw/misc/trace-events | 6 + > > hw/nvram/meson.build | 4 + > > hw/nvram/trace-events | 5 + > > tests/functional/meson.build | 2 + > > tests/functional/test_arm_aspeed_otp.py | 55 +++++++ > > 12 files changed, 530 insertions(+), 2 deletions(-) > > create mode 100644 include/hw/nvram/aspeed_otp.h > > create mode 100644 hw/nvram/aspeed_otp.c > > create mode 100644 tests/functional/test_arm_aspeed_otp.py > > > > I will queue patches 1-8,10 in aspeed-next. No need to resend. > > Please address the comments on patch 9 in a new series, Cc: Thomas. > > Thanks, > > C. > > > > >
