On Thu, Sep 4, 2025 at 7:14 PM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
>
>
> On 9/3/25 11:03 AM, Max Chou wrote:
> > The Zvqdotq extension is the vector dot-product extension of RISC-V.
> >
> > Signed-off-by: Max Chou <max.c...@sifive.com>
> > ---
> > target/riscv/cpu.c | 1 +
> > target/riscv/cpu_cfg_fields.h.inc | 1 +
> > target/riscv/tcg/tcg-cpu.c | 5 +++++
> > 3 files changed, 7 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index d055ddf462..95edd02e68 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -187,6 +187,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> > ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
> > ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
> > ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
> > + ISA_EXT_DATA_ENTRY(zvqdotq, PRIV_VERSION_1_12_0, ext_zvqdotq),
>
> Is this really 1.12? If it's marked as experimental I would expect it be a
> new
> extension, e.g. 1.13.
>
>
> Thanks,
>
> Daniel
>
Thanks for pointing out this part. I’ll update v4 for this.
Thanks,
Max
