On 16.09.2025 11:10, SillyZ wrote:
In PeliCAN mode reception, the RBS (Receive Buffer Status) bit
is set twice at line 842 and 845 with identical operations:
s->status_pel |= 0x01;
s->status_pel |= (1 << 0);
Between these two operations, only interrupt_pel is modified and
status_pel bit 4 is cleared, neither affecting bit 0. The second
operation is redundant.
This cleanup aligns PeliCAN mode with BasicCAN mode, which correctly
sets this bit only once (line 883).
Signed-off-by: SillyZ <1357816...@qq.com>
Reviewed-by: Michael Tokarev <m...@tls.msk.ru>
And applied to the trivial-patches tree.
Thanks,
/mjt
