On Thu, 7 Aug 2025 19:10:37 +0800 wangyuquan <wangyuquan1...@phytium.com.cn> wrote:
> From: Yuquan Wang <wangyuquan1...@phytium.com.cn> > > This creates a specific CXL host bridge (0001:00) with four cxl > root ports on sbsa-ref. And the memory layout provides separate > space windows for the cxl host bridge in the sbsa-ref memmap: > > - 64K CXL Host Bridge Component Registers (CHBCR) > - 64K CXL_PIO > - 128M CXL_MMIO > - 256M CXL_ECAM > - 4G CXL_MMIO_HIGH > > To provide CFMWs on sbsa-ref, this extends 1TB space from the > hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window: > > - 1T CXL_FIXED_WINDOW > > Signed-off-by: Yuquan Wang <wangyuquan1...@phytium.com.cn> This looks pretty standard to me so FWIW as someone who hasn't used the SBSA model. Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
