Hi Cédric > Subject: Re: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and > AST2700 > > On 9/18/25 11:08, Jamin Lin wrote: > > Hi Cédric > > > >> Subject: Re: [SPAM] [PATCH v3 00/14] Support PCIe RC to AST2600 and > >> AST2700 > >> > >> Hell Jamin, > >> > >> On 9/18/25 05:13, Jamin Lin wrote: > >>> v1: > >>> 1. Add PCIe PHY, CFG, and MMIO window support for AST2600. > >>> Note: Only supports RC_H. > >>> 2. Add PCIe PHY, CFG, and MMIO window support for AST2700. > >>> Note: Supports 3 RCs. > >>> > >>> v2: > >>> 1. Introduce a new root port device. > >>> 2. For AST2600 RC_H, add the root device at 80:00.0 and a root > >>> port at > >> 80.08.0 > >>> to match the real hardware topology, allowing users to attach > >>> PCIe > >> devices > >>> at the root port. > >>> 3. For AST2700, add a root port at 00.00.0 for each PCIe root > >>> complex to > >> match > >>> the real hardware topology, allowing users to attach PCIe > >>> devices at > >> the > >>> root port. > >>> > >>> v3: > >>> 1. Fix review issues. > >>> 2. update functional test for the e1000e network card. > >>> 3. update license header > >>> 4. Adding "Based on previous work from Cedric Le Goater, with > >>> Jamin's > >> summary > >>> implementation. > >> > >> v3 looks good. I only had a few comments on memory allocation > >> (g_autofree and MMIO alias regions) and on functional tests. > >> > >> v4 should be the last. > >> > > > > Thanks for your review and kindly support. > > Will resend v4 very soon. > > One last thing, the list of PCI capabilities reported on real HW is a little > different. See below. When you have time, it would be good to adjust the > model if possible. It can come later. >
Thanks for the suggestion and for reporting this issue. I’ll add it to my working queue. Here are the tasks currently in my queue: 1. Control coprocessor reset for AST2700 https://patchwork.kernel.org/project/qemu-devel/cover/20250717034054.1903991-1-jamin_...@aspeedtech.com/ 2. Analyze issue "func-arm-aspeed_ast2500 test occasionally times out" https://gitlab.com/qemu-project/qemu/-/issues/3117 3. Adjust PCIe capabilities 3. Support AST2700 IPC model(may require refactoring the INTC model if needed) 4. Support AST2700 A2 (planned for end of this year or Q1 next year) 5. Support AST2700 boot from BootMCU(RISC-V) instead of vbootrom, if a single binary ready. Thanks-Jamin > > Thanks, > > C. > > > > root@ast2600-default:~# lspci -vvv > 80:00.0 Host bridge: ASPEED Technology, Inc. Device 2600 > Subsystem: ASPEED Technology, Inc. Device 2600 > Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- > ParErr- Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- > <TAbort- <MAbort- >SERR- <PERR- INTx- > Latency: 0 > > 80:08.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge (rev 06) > (prog-if 00 [Normal decode]) > Subsystem: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- > ParErr+ Stepping- SERR+ FastB2B- DisINTx+ > Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- > <TAbort- <MAbort- >SERR- <PERR- INTx- > Latency: 0, Cache Line Size: 64 bytes > Interrupt: pin A routed to IRQ 82 > Bus: primary=80, secondary=81, subordinate=81, sec-latency=0 > I/O behind bridge: 1000-1fff [size=4K] [16-bit] > Memory behind bridge: 70000000-700fffff [size=1M] [32-bit] > Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff > [disabled] [64-bit] > Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- > <TAbort- <MAbort+ <SERR- <PERR- > BridgeCtl: Parity+ SERR+ NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- > PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- > Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ > Address: 000000001e77005c Data: 0000 > Capabilities: [78] Power Management version 3 > Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA > PME(D0+,D1+,D2+,D3hot+,D3cold+) > Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- > Capabilities: [80] Express (v2) Root Port (Slot-), IntMsgNum 0 > DevCap: MaxPayload 512 bytes, PhantFunc 0 > ExtTag+ RBE+ TEE-IO- > DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- > RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ > MaxPayload 128 bytes, MaxReadReq 512 bytes > DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ > TransPend- > LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit > Latency > L0s <1us, L1 <64us > ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ > LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk- > ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- > LnkSta: Speed 2.5GT/s, Width x1 > TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- > RootCap: CRSVisible- > RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ > CRSVisible- > RootSta: PME ReqID 0000, PMEStatus- PMEPending- > DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ > NROPrPrP- LTR- > 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- > EETLPPrefix- > EmergencyPowerReduction Not Supported, > EmergencyPowerReductionInit- > FRS- LN System CLS Not Supported, TPHComp- ExtTPHComp- > ARIFwd- > AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS- > DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- > AtomicOpsCtl: ReqEn- EgressBlck- > IDOReq- IDOCompl- LTR- EmergencyPowerReductionReq- > 10BitTagReq- OBFF Disabled, EETLPPrefixBlk- > LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- > Transmit Margin: Normal Operating Range, > EnterModifiedCompliance- ComplianceSOS- > Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB > preshoot > LnkSta2: Current De-emphasis Level: -3.5dB, > EqualizationComplete- > EqualizationPhase1- > EqualizationPhase2- EqualizationPhase3- > LinkEqualizationRequest- > Retimer- 2Retimers- CrosslinkRes: unsupported > Capabilities: [c0] Subsystem: ASPEED Technology, Inc. AST1150 PCI-to-PCI > Bridge > Capabilities: [100 v1] Virtual Channel > Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 > Arb: Fixed- WRR32- WRR64- WRR128- > Ctrl: ArbSelect=Fixed > Status: InProgress- > VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- > Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- > Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff > Status: NegoPending- InProgress- > Capabilities: [800 v1] Advanced Error Reporting > UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- > RxOF- MalfTLP- > ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- > AtomicOpBlocked- TLPBlockedErr- > PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- > PCRC_CHECK- TLPXlatBlocked- > UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- > RxOF- MalfTLP- > ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- > AtomicOpBlocked- TLPBlockedErr- > PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- > PCRC_CHECK- TLPXlatBlocked- > UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- > RxOF+ MalfTLP+ > ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- > AtomicOpBlocked- TLPBlockedErr- > PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- > PCRC_CHECK- TLPXlatBlocked- > CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- > AdvNonFatalErr- CorrIntErr- HeaderOF- > CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- > AdvNonFatalErr+ CorrIntErr- HeaderOF- > AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- > ECRCChkCap- ECRCChkEn- > MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- > HeaderLog: 00000000 00000000 00000000 00000000 > RootCmd: CERptEn- NFERptEn- FERptEn- > RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd- > FirstFatal- NonFatalMsg- FatalMsg- IntMsgNum 0 > ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000 > Kernel driver in use: pcieport > >
