From: Alistair Francis <[email protected]> The following changes since commit 29b77c1a2db2d796bc3847852a5c8dc2a1e6e83b:
Merge tag 'rust-ci-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2025-09-30 09:29:38 -0700) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20251003-3 for you to fetch changes up to ad2a0aa2824b1dac9f61bac33980e866e9a88856: docs: riscv-iommu: Update status of kernel support (2025-10-03 13:17:04 +1000) ---------------------------------------------------------------- First RISC-V PR for 10.2 * Fix MSI table size limit * Add riscv64 to FirmwareArchitecture * Sync RISC-V hwprobe with Linux * Implement MonitorDef HMP API * Update OpenSBI to v1.7 * Fix SiFive UART character drop issue and minor refactors * Fix RISC-V timer migration issues * Use riscv_cpu_is_32bit() when handling SBI_DBCN reg * Use riscv_csrr in riscv_csr_read * Align memory allocations to 2M on RISC-V * Do not use translator_ldl in opcode_at * Minor fixes of RISC-V CFI * Modify minimum VLEN rule * Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64 * Fixup IOMMU PDT Nested Walk * Fix endianness swap on compressed instructions * Update status of IOMMU kernel support ---------------------------------------------------------------- Andrea Bolognani (1): docs/interop/firmware: Add riscv64 to FirmwareArchitecture Andrew Jones (1): hw/riscv/riscv-iommu: Fix MSI table size limit Daniel Henrique Barboza (3): linux-user/syscall.c: sync RISC-V hwprobe with Linux target/riscv: implement MonitorDef HMP API roms/opensbi: Update to v1.7 Frank Chang (4): hw/char: sifive_uart: Raise IRQ according to the Tx/Rx watermark thresholds hw/char: sifive_uart: Avoid pushing Tx FIFO when size is zero hw/char: sifive_uart: Remove outdated comment about Tx FIFO hw/char: sifive_uart: Add newline to error message Guo Ren (Alibaba DAMO Academy) (1): hw/riscv/riscv-iommu: Fixup PDT Nested Walk Jim Shu (3): target/riscv: Fix the mepc when sspopchk triggers the exception target/riscv: Fix SSP CSR error handling in VU/VS mode target/riscv: Fix ssamoswap error handling Joel Stanley (1): docs: riscv-iommu: Update status of kernel support Max Chou (3): target/riscv: rvv: Replace checking V by checking Zve32x target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64 Philippe Mathieu-Daudé (1): target/riscv/kvm: Use riscv_cpu_is_32bit() when handling SBI_DBCN reg TANG Tiancheng (4): hw/intc: Save time_delta in RISC-V mtimer VMState migration: Add support for a variable-length array of UINT32 pointers hw/intc: Save timers array in RISC-V mtimer VMState target/riscv: Save stimer and vstimer in CPU vmstate Vladimir Isaev (1): target/riscv: do not use translator_ldl in opcode_at Xuemei Liu (1): qemu/osdep: align memory allocations to 2M on RISC-V stove (1): target/riscv: use riscv_csrr in riscv_csr_read vhaudiquet (1): target/riscv: Fix endianness swap on compressed instructions docs/interop/firmware.json | 4 +- docs/specs/riscv-iommu.rst | 35 +++--- include/hw/intc/riscv_aclint.h | 4 + include/migration/vmstate.h | 10 ++ include/qemu/osdep.h | 2 +- target/riscv/cpu.h | 3 +- target/riscv/helper.h | 21 ++-- hw/char/sifive_uart.c | 36 +++--- hw/intc/riscv_aclint.c | 7 +- hw/riscv/riscv-iommu.c | 154 ++++++++++++++++++++++++- linux-user/syscall.c | 89 ++++++++++++++ target/riscv/cpu.c | 2 +- target/riscv/csr.c | 5 +- target/riscv/kvm/kvm-cpu.c | 2 +- target/riscv/machine.c | 28 ++++- target/riscv/op_helper.c | 49 ++++++++ target/riscv/riscv-qmp-cmds.c | 148 ++++++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 21 +++- target/riscv/translate.c | 3 +- target/riscv/vector_helper.c | 20 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 50 +++++++- target/riscv/insn_trans/trans_rvzce.c.inc | 6 +- target/riscv/insn_trans/trans_rvzicfiss.c.inc | 9 ++ pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 268312 -> 268752 bytes pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 272504 -> 273048 bytes roms/opensbi | 2 +- 26 files changed, 625 insertions(+), 85 deletions(-)
