In preparation of having RISC-V cores changing their endianness at runtime, centralize the MO_TE uses to a pair of methods.
Except the 128-bit LD/ST change (first patch), no further functional changes intended. Philippe Mathieu-Daudé (13): target/riscv: Really use little endianness for 128-bit loads/stores target/riscv: Explode MO_TExx -> MO_TE | MO_xx target/riscv: Conceal MO_TE within gen_amo() target/riscv: Conceal MO_TE within gen_inc() target/riscv: Conceal MO_TE within gen_load() / gen_store() target/riscv: Conceal MO_TE within gen_load_idx() / gen_store_idx() target/riscv: Conceal MO_TE within gen_fload_idx() / gen_fstore_idx() target/riscv: Conceal MO_TE within gen_storepair_tl() target/riscv: Conceal MO_TE within gen_cmpxchg*() target/riscv: Conceal MO_TE|MO_ALIGN within gen_lr() / gen_sc() target/riscv: Factor MemOp variable out when MO_TE is set target/riscv: Introduce mo_endian() helper target/riscv: Introduce mo_endian_env() helper target/riscv/op_helper.c | 28 ++++-- target/riscv/translate.c | 16 ++- target/riscv/insn_trans/trans_rva.c.inc | 50 +++++----- target/riscv/insn_trans/trans_rvd.c.inc | 6 +- target/riscv/insn_trans/trans_rvf.c.inc | 6 +- target/riscv/insn_trans/trans_rvi.c.inc | 36 ++++--- target/riscv/insn_trans/trans_rvzabha.c.inc | 20 ++-- target/riscv/insn_trans/trans_rvzacas.c.inc | 12 ++- target/riscv/insn_trans/trans_rvzce.c.inc | 12 ++- target/riscv/insn_trans/trans_rvzfh.c.inc | 8 +- target/riscv/insn_trans/trans_rvzicfiss.c.inc | 10 +- target/riscv/insn_trans/trans_xthead.c.inc | 98 ++++++++++--------- 12 files changed, 181 insertions(+), 121 deletions(-) -- 2.51.0
