From: Luc Michel <[email protected]> Refactor the CRL device creation using the VersalMap structure. The connections to the RPU CPUs are temporarily removed and will be reintroduced with next refactoring commits.
Signed-off-by: Luc Michel <[email protected]> Reviewed-by: Francisco Iglesias <[email protected]> Reviewed-by: Edgar E. Iglesias <[email protected]> Tested-by: Philippe Mathieu-Daudé <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]> --- include/hw/arm/xlnx-versal.h | 3 --- hw/arm/xlnx-versal.c | 36 +++++++++++++++++++----------------- 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 5a685aea6d4..d3ce13e69de 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -17,7 +17,6 @@ #include "hw/cpu/cluster.h" #include "hw/intc/arm_gicv3.h" #include "qom/object.h" -#include "hw/misc/xlnx-versal-crl.h" #include "net/can_emu.h" #include "target/arm/cpu.h" #include "hw/arm/xlnx-versal-version.h" @@ -71,8 +70,6 @@ struct Versal { CPUClusterState cluster; ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; } rpu; - - XlnxVersalCRL crl; } lpd; struct { diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 81adf8d35b6..f5f98a3030d 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -42,6 +42,7 @@ #include "hw/misc/xlnx-versal-cfu.h" #include "hw/misc/xlnx-versal-cframe-reg.h" #include "hw/or-irq.h" +#include "hw/misc/xlnx-versal-crl.h" #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") @@ -151,6 +152,8 @@ typedef struct VersalMap { uint32_t blktype_frames[7]; } cframe_cfg[15]; } cfu; + + VersalSimplePeriphMap crl; } VersalMap; static const VersalMap VERSAL_MAP = { @@ -215,6 +218,8 @@ static const VersalMap VERSAL_MAP = { { { 38498, 3841, 15361, 13, 7, 3, 1 } }, }, }, + + .crl = { 0xff5e0000, 10 }, }; static const VersalMap *VERSION_TO_MAP[] = { @@ -1115,27 +1120,24 @@ static void versal_create_cfu(Versal *s, const struct VersalCfuMap *map) sysbus_mmio_get_region(sbd, 0)); } -static void versal_create_crl(Versal *s, qemu_irq *pic) +static inline void versal_create_crl(Versal *s) { - SysBusDevice *sbd; - int i; + const VersalMap *map; + const char *crl_class; + DeviceState *dev; - object_initialize_child(OBJECT(s), "crl", &s->lpd.crl, - TYPE_XLNX_VERSAL_CRL); - sbd = SYS_BUS_DEVICE(&s->lpd.crl); + map = versal_get_map(s); - for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { - g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i); + crl_class = TYPE_XLNX_VERSAL_CRL; + dev = qdev_new(crl_class); + object_property_add_child(OBJECT(s), "crl", OBJECT(dev)); - object_property_set_link(OBJECT(&s->lpd.crl), - name, OBJECT(&s->lpd.rpu.cpu[i]), - &error_abort); - } + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_abort); - sysbus_realize(sbd, &error_fatal); - memory_region_add_subregion(&s->mr_ps, MM_CRL, - sysbus_mmio_get_region(sbd, 0)); - sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); + memory_region_add_subregion(&s->mr_ps, map->crl.addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); + + versal_sysbus_connect_irq(s, SYS_BUS_DEVICE(dev), 0, map->crl.irq); } /* This takes the board allocated linear DDR memory and creates aliases @@ -1338,8 +1340,8 @@ static void versal_realize(DeviceState *dev, Error **errp) versal_create_trng(s, &map->trng); versal_create_rtc(s, &map->rtc); versal_create_cfu(s, &map->cfu); + versal_create_crl(s); - versal_create_crl(s, pic); versal_map_ddr(s); versal_unimp(s); -- 2.43.0
