On Mon, Aug 11, 2025 at 1:59 PM Yang Jialong <[email protected]> wrote: > > 4.5.4. Supervisor MSI address configuration (smsiaddrcfg and > smsiaddrcfgh) > smsiaddrcfgh: > bits 22:20 LHXS(WARL) > bits 11:0 High Base PPN(WARL) > > Signed-off-by: Yang Jialong <[email protected]>
This fails to build as there is still a APLIC_xMSICFGADDRH_VALID_MASK user ../hw/intc/riscv_aplic.c: In function ‘riscv_aplic_set_kvm_msicfgaddr’: ../hw/intc/riscv_aplic.c:191:34: error: ‘APLIC_xMSICFGADDRH_VALID_MASK’ undeclared (first use in this function); did you mean ‘APLIC_MMSICFGADDRH_VALID_MASK’? 191 | APLIC_xMSICFGADDRH_VALID_MASK; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | APLIC_MMSICFGADDRH_VALID_MASK ../hw/intc/riscv_aplic.c:191:34: note: each undeclared identifier is reported only once for each function it appears in https://gitlab.com/alistair23/qemu/-/jobs/11528885170 Alistair > --- > hw/intc/riscv_aplic.c | 27 +++++++++++++++++---------- > 1 file changed, 17 insertions(+), 10 deletions(-) > > v1 --> v2: > - fix calculation of MSI address. > - In Supervisor mode, lhxw/hhxs/hhxw fields are in mmsiaddrcfgh register. > - And lhxs field is in smsiaddrcfgh. > > diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c > index a1d9fa5085..2dd54cafaa 100644 > --- a/hw/intc/riscv_aplic.c > +++ b/hw/intc/riscv_aplic.c > @@ -96,7 +96,7 @@ > (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \ > APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs)) > > -#define APLIC_xMSICFGADDRH_VALID_MASK \ > +#define APLIC_MMSICFGADDRH_VALID_MASK \ > (APLIC_xMSICFGADDRH_L | \ > (APLIC_xMSICFGADDRH_HHXS_MASK << APLIC_xMSICFGADDRH_HHXS_SHIFT) | \ > (APLIC_xMSICFGADDRH_LHXS_MASK << APLIC_xMSICFGADDRH_LHXS_SHIFT) | \ > @@ -104,6 +104,10 @@ > (APLIC_xMSICFGADDRH_LHXW_MASK << APLIC_xMSICFGADDRH_LHXW_SHIFT) | \ > APLIC_xMSICFGADDRH_BAPPN_MASK) > > +#define APLIC_SMSICFGADDRH_VALID_MASK \ > + ((APLIC_xMSICFGADDRH_LHXS_MASK << APLIC_xMSICFGADDRH_LHXS_SHIFT) | \ > + APLIC_xMSICFGADDRH_BAPPN_MASK) > + > #define APLIC_SETIP_BASE 0x1c00 > #define APLIC_SETIPNUM 0x1cdc > > @@ -409,13 +413,8 @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic, > msicfgaddr = aplic->kvm_msicfgaddr; > msicfgaddrH = ((uint64_t)aplic->kvm_msicfgaddrH << 32); > } else { > - if (aplic->mmode) { > - msicfgaddr = aplic_m->mmsicfgaddr; > - msicfgaddrH = aplic_m->mmsicfgaddrH; > - } else { > - msicfgaddr = aplic_m->smsicfgaddr; > - msicfgaddrH = aplic_m->smsicfgaddrH; > - } > + msicfgaddr = aplic_m->mmsicfgaddr; > + msicfgaddrH = aplic_m->mmsicfgaddrH; > } > > lhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) & > @@ -427,6 +426,14 @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic, > hhxw = (msicfgaddrH >> APLIC_xMSICFGADDRH_HHXW_SHIFT) & > APLIC_xMSICFGADDRH_HHXW_MASK; > > + if (!aplic->kvm_splitmode && !aplic->mmode) { > + msicfgaddrH = aplic_m->smsicfgaddrH; > + msicfgaddr = aplic_m->smsicfgaddr; > + > + lhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) & > + APLIC_xMSICFGADDRH_LHXS_MASK; > + } > + > group_idx = hart_idx >> lhxw; > > addr = msicfgaddr; > @@ -771,7 +778,7 @@ static void riscv_aplic_write(void *opaque, hwaddr addr, > uint64_t value, > } else if (aplic->mmode && aplic->msimode && > (addr == APLIC_MMSICFGADDRH)) { > if (!(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { > - aplic->mmsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK; > + aplic->mmsicfgaddrH = value & APLIC_MMSICFGADDRH_VALID_MASK; > } > } else if (aplic->mmode && aplic->msimode && > (addr == APLIC_SMSICFGADDR)) { > @@ -792,7 +799,7 @@ static void riscv_aplic_write(void *opaque, hwaddr addr, > uint64_t value, > (addr == APLIC_SMSICFGADDRH)) { > if (aplic->num_children && > !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) { > - aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK; > + aplic->smsicfgaddrH = value & APLIC_SMSICFGADDRH_VALID_MASK; > } > } else if ((APLIC_SETIP_BASE <= addr) && > (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) { > -- > 2.34.1 > >
