Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/tcg/tlb-insns.c | 53 ++++++++++++++++++++++++++++----------
1 file changed, 39 insertions(+), 14 deletions(-)
diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c
index cbab7f81f9..c7583957b0 100644
--- a/target/arm/tcg/tlb-insns.c
+++ b/target/arm/tcg/tlb-insns.c
@@ -1073,10 +1073,17 @@ static void tlbi_aa64_rvae3_write(CPUARMState *env,
* since we don't support flush-for-specific-ASID-only or
* flush-last-level-only.
*/
-
do_rvae_write(env, value, vae3_tlbmask(), tlb_force_broadcast(env));
}
+static void tlbi_aa64_rvae3_write128(CPUARMState *env,
+ const ARMCPRegInfo *ri,
+ uint64_t vallo, uint64_t valhi)
+{
+ do_rvae_write128(env, vallo, valhi, vae3_tlbmask(),
+ tlb_force_broadcast(env));
+}
+
static void tlbi_aa64_rvae3is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
uint64_t value)
@@ -1087,10 +1094,16 @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env,
* since we don't support flush-for-specific-ASID-only,
* flush-last-level-only or inner/outer specific flushes.
*/
-
do_rvae_write(env, value, vae3_tlbmask(), true);
}
+static void tlbi_aa64_rvae3is_write128(CPUARMState *env,
+ const ARMCPRegInfo *ri,
+ uint64_t vallo, uint64_t valhi)
+{
+ do_rvae_write128(env, vallo, valhi, vae3_tlbmask(), true);
+}
+
static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -1265,28 +1278,40 @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
.write128fn = tlbi_aa64_rvae2_write128 },
{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
- .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
- .writefn = tlbi_aa64_rvae3is_write },
+ .access = PL3_W,
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae3is_write,
+ .write128fn = tlbi_aa64_rvae3is_write128 },
{ .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5,
- .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
- .writefn = tlbi_aa64_rvae3is_write },
+ .access = PL3_W,
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae3is_write,
+ .write128fn = tlbi_aa64_rvae3is_write128 },
{ .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1,
- .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
- .writefn = tlbi_aa64_rvae3is_write },
+ .access = PL3_W,
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae3is_write,
+ .write128fn = tlbi_aa64_rvae3is_write128 },
{ .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5,
- .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
- .writefn = tlbi_aa64_rvae3is_write },
+ .access = PL3_W,
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae3is_write,
+ .write128fn = tlbi_aa64_rvae3is_write128 },
{ .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1,
- .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
- .writefn = tlbi_aa64_rvae3_write },
+ .access = PL3_W,
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae3_write,
+ .write128fn = tlbi_aa64_rvae3_write128 },
{ .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
- .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
- .writefn = tlbi_aa64_rvae3_write },
+ .access = PL3_W,
+ .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_128BIT,
+ .writefn = tlbi_aa64_rvae3_write,
+ .write128fn = tlbi_aa64_rvae3_write128 },
};
static const ARMCPRegInfo tlbios_reginfo[] = {
--
2.43.0
