From: Jim Shu <[email protected]> In VU/VS mode, accessing $ssp CSR will trigger the virtual instruction exception instead of illegal instruction exception if SSE is disabled via xenvcfg CSRs.
This is from RISC-V CFI v1.0 spec ch2.2.4. Shadow Stack Pointer Signed-off-by: Jim Shu <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> (cherry picked from commit 84c1605b7606d810ded4c1c3a2717f158dc89e3f) Signed-off-by: Michael Tokarev <[email protected]> diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 76e2f7e1d5..76e77ae2d1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -202,6 +202,8 @@ static RISCVException cfi_ss(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) if (env->debugger) { return RISCV_EXCP_NONE; + } else if (env->virt_enabled) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } #endif return RISCV_EXCP_ILLEGAL_INST; -- 2.47.3
