On Tue, 9 Sept 2025 at 23:11, Yubin Zou <[email protected]> wrote: > > From: Titus Rwantare <[email protected]> > > This switches to a using a fully sized PCI memory region that's > separate from system memory. Accesses to this PCI memory region are > gated by the AXI to PCIe windows whose size and offsets are validated. > > - PCIe config space is not necessarily aliased with PCIe mmio space. > Ignore translation addresses for config space windows. > - Make window configuration register writes order independent. > > Tested with pci-testdev.
I'm in general not a fan of introducing something in one patch and then "reworking" it in a later patch in the same series. It's usually easier to understand and review if you implement it the right way the first time. thanks -- PMM
