Removed one patch from the patch set: hw/pci: Allow explicit function numbers in pci since it is merged to master branch.
I addressed several comments in this version and rebased on top of latest master. Djordje Todorovic (13): hw/intc: Allow gaps in hartids for aclint and aplic target/riscv: Add cpu_set_exception_base target/riscv: Add MIPS P8700 CPU target/riscv: Add MIPS P8700 CSRs target/riscv: Add mips.ccmov instruction target/riscv: Add mips.pref instruction target/riscv: Add Xmipslsp instructions hw/misc: Add RISC-V CMGCR device implementation hw/misc: Add RISC-V CPC device implementation hw/riscv: Add support for RISCV CPS hw/riscv: Add support for MIPS Boston-aia board mode riscv/boston-aia: Add an e1000e NIC in slot 0 func 1 test/functional: Add test for boston-aia board configs/devices/riscv64-softmmu/default.mak | 1 + docs/system/riscv/mips.rst | 20 + docs/system/target-riscv.rst | 1 + hw/intc/riscv_aclint.c | 18 +- hw/intc/riscv_aplic.c | 13 +- hw/misc/Kconfig | 17 + hw/misc/meson.build | 3 + hw/misc/riscv_cmgcr.c | 248 +++++++++ hw/misc/riscv_cpc.c | 265 ++++++++++ hw/riscv/Kconfig | 6 + hw/riscv/boston-aia.c | 477 ++++++++++++++++++ hw/riscv/cps.c | 196 +++++++ hw/riscv/meson.build | 3 + include/hw/misc/riscv_cmgcr.h | 50 ++ include/hw/misc/riscv_cpc.h | 64 +++ include/hw/riscv/cps.h | 66 +++ target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 42 ++ target/riscv/cpu.h | 7 + target/riscv/cpu_cfg.h | 5 + target/riscv/cpu_cfg_fields.h.inc | 3 + target/riscv/cpu_vendorid.h | 1 + target/riscv/insn_trans/trans_xmips.c.inc | 136 +++++ target/riscv/meson.build | 2 + target/riscv/mips_csr.c | 217 ++++++++ target/riscv/translate.c | 3 + target/riscv/xmips.decode | 35 ++ tests/functional/riscv64/meson.build | 1 + .../functional/riscv64/test_riscv64_boston.py | 164 ++++++ 29 files changed, 2060 insertions(+), 5 deletions(-) create mode 100644 docs/system/riscv/mips.rst create mode 100644 hw/misc/riscv_cmgcr.c create mode 100644 hw/misc/riscv_cpc.c create mode 100644 hw/riscv/boston-aia.c create mode 100644 hw/riscv/cps.c create mode 100644 include/hw/misc/riscv_cmgcr.h create mode 100644 include/hw/misc/riscv_cpc.h create mode 100644 include/hw/riscv/cps.h create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc create mode 100644 target/riscv/mips_csr.c create mode 100644 target/riscv/xmips.decode create mode 100755 tests/functional/riscv64/test_riscv64_boston.py -- 2.34.1
