On Wed, Oct 15, 2025 at 6:39 AM Anton Johansson via <[email protected]> wrote: > > The field only holds values of 2 and 3, fix its size to 8 bits and > update stores from TCG. > > Signed-off-by: Anton Johansson <[email protected]> > Reviewed-by: Pierrick Bouvier <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.h | 2 +- > target/riscv/translate.c | 4 ++-- > target/riscv/insn_trans/trans_rvi.c.inc | 8 ++++---- > target/riscv/insn_trans/trans_rvzicfiss.c.inc | 4 ++-- > 4 files changed, 9 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 6bee15cb5e..37035a9541 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -259,7 +259,7 @@ struct CPUArchState { > /* env place holder for extra word 2 during unwind */ > uint64_t excp_uw2; > /* sw check code for sw check exception */ > - target_ulong sw_check_code; > + uint8_t sw_check_code; > #ifdef CONFIG_USER_ONLY > uint32_t elf_flags; > #endif > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 14c8f1c6a2..ca7e6c44c6 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -1362,8 +1362,8 @@ static void riscv_tr_translate_insn(DisasContextBase > *dcbase, CPUState *cpu) > if (ctx->fcfi_lp_expected) { > /* Emit after insn_start, i.e. before the op following insn_start. */ > tcg_ctx->emit_before_op = QTAILQ_NEXT(ctx->base.insn_start, link); > - tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > - tcg_env, offsetof(CPURISCVState, sw_check_code)); > + tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > + tcg_env, offsetof(CPURISCVState, sw_check_code)); > gen_helper_raise_exception(tcg_env, > tcg_constant_i32(RISCV_EXCP_SW_CHECK)); > tcg_ctx->emit_before_op = NULL; > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc > b/target/riscv/insn_trans/trans_rvi.c.inc > index 9c8c04b2dc..5efdd95f97 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -53,8 +53,8 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) > /* > * misaligned, according to spec we should raise sw check exception > */ > - tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > - tcg_env, offsetof(CPURISCVState, sw_check_code)); > + tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > + tcg_env, offsetof(CPURISCVState, sw_check_code)); > gen_helper_raise_exception(tcg_env, > tcg_constant_i32(RISCV_EXCP_SW_CHECK)); > return true; > @@ -66,8 +66,8 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) > TCGv tmp = tcg_temp_new(); > tcg_gen_extract_tl(tmp, get_gpr(ctx, xT2, EXT_NONE), 12, 20); > tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->label, skip); > - tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > - tcg_env, offsetof(CPURISCVState, sw_check_code)); > + tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > + tcg_env, offsetof(CPURISCVState, sw_check_code)); > gen_helper_raise_exception(tcg_env, > tcg_constant_i32(RISCV_EXCP_SW_CHECK)); > gen_set_label(skip); > diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc > b/target/riscv/insn_trans/trans_rvzicfiss.c.inc > index fa1489037d..3f71adec35 100644 > --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc > +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc > @@ -40,8 +40,8 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk > *a) > mxl_memop(ctx) | MO_ALIGN); > TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE); > tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip); > - tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_BCFI_TVAL), > - tcg_env, offsetof(CPURISCVState, sw_check_code)); > + tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_BCFI_TVAL), > + tcg_env, offsetof(CPURISCVState, sw_check_code)); > gen_update_pc(ctx, 0); > gen_helper_raise_exception(tcg_env, > tcg_constant_i32(RISCV_EXCP_SW_CHECK)); > -- > 2.51.0 > >
