This patchset introduces cache enumeration and two vCPU models (Client and Server) for the Zhaoxin "Shijidadao" architecture. With these additions, QEMU can expose the core identity and features of this architecture without relying on host-passthrough.
There are several points that may need particular attention from maintainers: 1. The Shijidadao-Client model uses '.version = 1' to represent the hardware v1 revision, with 'version=2' added to capture v2 differences. Please check whether this usage aligns with existing versioning practices. 2. For both Shijidadao-Client and Shijidadao-Server, the "x-force-cpuid-0x1f" feature is placed under the version 1 definition. At present there is no mechanism to represent this feature via `.features[index]` in the default model definition, so attaching it to v1 is the only available option. Feedback on whether this placement is acceptable would be appreciated. 3. The Shijidadao-Server model enables the 'core-capability' bit by default, but KVM does not yet virtualize the corresponding MSR. Guidance on whether this setting should remain in the model is requested. Thanks for your time reviewing this series! Ewan Hai (3): target/i386: Add cache model for Zhaoxin Shijidadao vCPUs target/i386: Introduce Zhaoxin Shijidadao-Client CPU model target/i386: Introduce Zhaoxin Shijidadao-Server CPU model target/i386/cpu.c | 385 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 385 insertions(+) -- 2.34.1
