On Mon, 6 Oct 2025 at 01:10, Gustavo Romero <[email protected]> wrote: > > Add all FEAT_MEC registers. Enable access to the registers via the > SCTLR2 and TCR2 control bits. Add the two new cache management > instructions, which are nops in QEMU because we do not model caches. > > Message-ID: <[email protected]> > Reviewed-by: Richard Henderson <[email protected]> > [rth: Squash 3 patches to add all registers at once.] > Signed-off-by: Richard Henderson <[email protected]> > Signed-off-by: Gustavo Romero <[email protected]>
Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
